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Fraunhofer Gesellschaft is one of the top 10 employers for beginning scientists and engineers in Germany. The „Fraunhofer Research Institution for Modular Solid State Technologies EMFT“ located in Munich, Germany, offers the following position:
Marie Curie Scholarship - Experienced Researcher, still in their early career (PostDoc)
Integration technologies for flexible electronic systems - manufacture and reliability in the CONTEST Collaborative Network for Training in Electronic Skin Technology http://www.contest-itn.eu/
Requirements:
PhD -degree OR Research experience of
4* years or more preferred in one of the following disciplines: engineering, physics, material science, process technology or similar
AND research experience less than 5* years.
* (1) & (2) counted from the diploma that gives the rights to embark in a doctoral degree
Mobility rule:
The researcher must not have resided or carried out his/her main activity (work, studies, etc) in Germany for more than 12 months in the 3 years immediately prior to his/her recruitment. Short stays, such as holidays, are not taken into account.
All requirements need to be fulfilled. This is due to the European regulations for "Marie Curie Initial Training Network Programme".
Your tasks:
Assessing the risk of electrostatic discharge ESD for electronic skin during flex-integration and use, developing sensors and associated electronic circuits including a hierarchical protection scheme in order to increase the robustness of the embedded electronics.
General Requirements:
This position is sponsored by the European Community in the framework of “Marie Curie Initial Training Networks". Conditions for the employment are linked to specific regulations of the European Union. The position is limited to 2 years.
You will find an experienced, broad-minded and motivated team which will give you strong support and enable you to work self-reliant.
General:
Severely diabled persons with similarly eligibility fpr employment will be hired preferential. The Fraunhofer-Gesellschaft attaches importance to gender equality in career.
Contact:
Please send your application both to the website of the Marie Curie project CONTEST and Fraunhofer EMFT:
Fraunhofer-Einrichtung für Modulare Festkörper-Technologien EMFT
Elke Berger
Hansastraße 27 d
80686 München
or by E-Mail at: elke.berger@emft.fraunhofer.de
Fragen zu dieser Position beantwortet gerne:
Technical questions related to this position will be answered by:
Technical questions related to this position will be answered by:
Dr. Horst Gieser
Phone +49 (89) 54759-520
horst.gieser@emft.fraunhofer.de
More information about the institute:
http://www.emft.fraunhofer.de
Posted 5-22-2013 |
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ESD Circuit Design Engineer - San Diego
Qualcomm CDMA Technologies (QCT www.qualcomm.com/qct) is the largest developer of 3G and 4G communication technology in the world and is consistently ranked near the top of Fortune's list of "100 Best Companies to Work For." Our Digital ASIC design team delivers cutting edge hardware and software products across every established wireless standard/protocol, and is currently seeking applicants for positions focused on ESD Circuit Design, verification, characterization, validation, and modeling and library view generation.
- ESD Circuit design for: GPIO, HSI, DDRx, SD, SLIMBus and high speed IOs, Digital & Analog & RF Hard Macros (DAC, PLL, BBRx, RF modules, LNA, etc)
- ESD Design for top level chips Digital, Analog, RF, mixed Signal and package.
- Post Layout Extraction & Simulation, testing in conjunction with silicon validation.
- TLP/VFTLP Testing, Characterization of new design and for debugging purposes.
- IO Circuit design
- Silicon validation and debugging of ESD failures along with RMA analysis
- Working with Layout designers, Packaging team and Reliability team for designing, testing and meeting JEDEC specification as far as ESD & Latchup is concerned.
- 3+ years of industry experience using Hspice/Finesim (or any other Industry standard) Spice simulator.
- ESD Circuit Design and Latchup, along with debugging and FA.
- General Purpose I/O circuit Design.
- Transistor level circuit design/analysis knowledge (Analog & Digital) is required.
- Must have prior experience with Cadence circuit design tools (Schematic, Analog Artist, and Layout).
- Experience with commercial IP/ASIC views and flows are required.
- Experience in writing Spice stimulus, measurement files and IBIS modeling is highly valued.
- Familiarity with Version Control tools is a plus.
- Good communication and teamwork skills.
- Familiarity with generating views for ASIC design such as LEF, Apache views for IR drop analysis and LPE extraction is a plus.
- In depth knowledge of full custom layout and experience working closely with mask designers
- Understanding of High Speed I/Os & specialty I/Os such as DDR, HSI, SLIMBus and SD I/Os is highly valued.
- Ability to write shell scripts (PERL preferred) to automate circuit design tasks and for general text parsing/manipulation.
- Knowledge of different IC package types (FlipChip, Wirebond, WLP) and associated ESD protection
- Ability to efficiently work on multiple projects simultaneously.
To Apply Click Here
posting extended |
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NXP Semiconductors
ESD Engineer
Location: The Netherlands - Nijmegen
Experience Level: 5-10 years
Education Level: Masters Degree
Type of Function: Full-Time
Organization Description:
NXP Semiconductors N.V. (NASDAQ: NXPI) provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management, Interface, Security, Digital Processing and Manufacturing expertise. These innovations are used in a wide range of automotive, industrial, consumer, lighting, medical, computing and identification applications. A global semiconductor company with operations in more than 25 countries, NXP posted revenue of USD 4.4 billion in 2010. Additional information can be found by visiting www.nxp.com.
Foundation Design IP is part of the world-wide central Research & Development organization of NXP Semiconductors. We enable and support the high-performance mixed signal product innovation with our NXP product divisions. Our people excite our customers by delivering foundation design IP, like input/output interfaces (IOs) with superior ESD performance.
Your Responsibilities:
As ESD engineer involved in the innovation program on IO design within the Foundation Design IP group. The focus of the innovation program is on differentiating low voltage/high speed IO design in advanced CMOS, RF and High Voltage technology nodes. You define and design new solutions to adhere to ESD requirements on system as well as circuit level, e.g. according challenging HBM and CDM standards. You test the susceptibility of the devices using the most advanced ESD test tools. You keep abreast of technical, application, market and competition developments in the relevant technology domain, showing understanding of the NXP business interests. Support product design teams to define customized IO/ESD solutions.
Key areas of responsibility are:
- Responsible for the research & development of analog, mixed signal circuits and layouts of low voltage/high speed IO designs with superior ESD performance. Ensure that project results meet agreed specifications, schedule and quality standards of NXP’s business needs.
- Electrical verification of developed circuits through advanced device/circuit simulations and correlation to actual silicon measurements.
- Implement innovative solutions of high performance analog circuits in IO/ESD designs, self and through others. Publish the results and write invention disclosures.
Your Profile:
- Ph.D. in Physics or MSc EE (Analog)
- Working experience (> 5 years) in preferably IO/ESD design of Analog Mixed-Signal IC’s.
- Good knowledge of semiconductor physics in general.
- You fit in an industrial development environment where a combination of project driven and innovation activities generate transferable results for our business.
- Very analytical in nature and able to work in a multi-disciplinary environment.
- Creative, out-of-the-box thinker with a high level of personal involvement.
- Strong theoretical background with a pragmatic approach.
- Good communication skills and fluent in English
Contact:
Andre Montree, e-mail:andre.montree@nxp.com, phone +31 (0)6 129 94 022
Updated on 4/9/2013 |
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Accelerate Your Future...Be Part of the Foundry of the Future
Become part of GLOBALFOUNDRIES Singapore
We are looking for motivated and skilled people who want to be part of a diverse and global organisation that is reshaping the landscape of the foundry industry.
GLOBALFOUNDRIES is the world’s true global foundry. Headquartered in Silicon Valley, California with manufacturing operations in Singapore, Germany and soon to open, New York; GLOBALFOUNDRIES has a diverse, international workforce united to become the foundry of choice for the world’s leading fabless companies and integrated device manufacturers (IDM). With a strong market position, technology leadership, and financial staying power, GLOBALFOUNDRIES is well positioned to succeed in the growing foundry industry.
GLOBALFOUNDRIES Singapore (formerly Chartered Semiconductor Manufacturing Ltd) is one of the key manufacturing and operation sites for GLOBALFOUNDRIES. With 200mm and 300mm wafer manufacturing facilities, GLOBALFOUNDRIES Singapore provides a diverse product portfolio to address the mainstream technologies and advanced technology down to 40nm processes. In addition, to manufacturing, GLOBALFOUNDRIES Singapore houses corporate functions in Design Enablement, Marketing, Customer Engineering, Enterprise IT, and Customer Support.
Tapping on a world-wide workforce, GLOBALFOUNDRIES has an open environment that values diversity in culture, ideas, and people. So come join us and realize your potential and be part of a global organization that offers opportunities, a vision, and an environment for success. Be part of GLOBALFOUNDRIES Singapore.
TD - Senior Engineer / Engineer (ESD)
(Singapore)
Responsibilities:
Senior Engineer
- Assist in the ESD and LU development support for various technology nodes
- The job scope will include extensive test chip design and layout, spice model development, circuit simulations, layout verification, design database preparation and documentation
- The job scope includes R&D on new and optimized ESD solutions from a foundry perspective
- In this position, the staff will be support cross functionally teams such as IO design and ESD library development
Other responsibilities will include:
- Investigates and develops solution for highly complex circuit level ESD problems
- Learn and evolve in any other skills and tools required to achieve challenging ESD development goals including automation, and new research areas
- Publish in relevant peer reviewed journal and conferences
- Actively pursue patent development
Engineer
- The engineer will actively pursue ESD device development and assessment of ESD and LU performance of various technologies
- The responsibilities include device definition, characterization of the ESD devices using DC, pulsed and RF testers, latch up characterization, documentation and reporting, assist internal process owners for the ESD and LU rule definition
Other responsibilities include:
- As required, explore the need to modify any given processes, procedures or methods to develop new solutions for the foundry and its customers
- Continuously research and potentially develop new test methods and charactersation approaches.
- Publish in relevant peer reviewed journal and conferences
- Actively pursue patent development
Requirements:
- Phd or Masters Degree in Physics
- 2 to 5 years of relevant working experience
Senior Engineer
- Good and demonstrated knowledge in device layout, circuit design, custom layout, and IO design
- Well versed in circuit design and layout tools (such as those from cadence or Mentor)
- Analog circuit and RF design knowledge is a plus
Engineer
- Good knowledge of microelectronics and semiconductor device physics
- Demonstrated expertise and knowledge in ESD protection design and analysis using pulsed/ ESD testers, and device design
- Experience in HV device physics, compact model simulation, and product engineering is valuable
- Candidate is required to have exceptional technical skills combined with evidence of motivation to work in ESD and LU reliability area
- Open and willing to listen to internal and external customer concerns and willing to go an extra mile to help customers succeed in their efforts to achieve required ESD and LU performance targets
- Fluency in English language is a must, with good comprehension capability
- Ability to handle anyone with a pleasant attitude and willingness to share/mentor colleagues
We regret that only shortlisted candidates will be notified.
Interested applicants, please apply through vivienlye@globalfoundries.com
Posting extended
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| Positions Wanted |
| To post a resume contact: info@esda.org (ESDA members only) |
| Name: Leo G. Henry |
Position Wanted: ESD Professional who can work in the following
disciplines: Engineer, Consultant, Test or Reliability. |
| Contact:
leogesd@pacbell.net |
| Resume: Download Resume |
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| Name: Arnold J. Steinman |
| Position Wanted: Electrostatics Consultant |
| Resume: Download Resume |
      
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