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• Workshop A1. ESD Protection Targets
  Moderator: Charvaka Duvvury, Texas Instruments

  In light of the work from the Industry Council on ESD Target Levels it has become clear that the ESD protection designs for the IC pins may be carrying an unnecessary burden. This burden becomes a problem when the IC circuits are trying to meet speed and performance demands. Through this workshop we will review the current ESD requirements for HBM, MM and CDM and discuss the reasons why this load must be shifted to better ESD control methods while defining the realistic specification targets for each stress model. The audience participation will be involved to address the following questions. What are the realistic component IC ESD requirements? How should the ESD designers and IC designers work together to achieve these? At what levels do the designs become impossible? What types of circuits are intolerable to even minimum ESD targets? Are the ESD designers responsible for system level protection also?

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• Workshop A2. Controlling ESD in the Modern Cleanroom Manufacturing Environment (Cleanrooms / ESD / Ionization Guidelines and Considerations)
  Moderator: Kevin Duncan, Seagate

  As devices become faster and feature sizes decrease, sensitivities to ESD and contamination increase. This workshop will focus on the roles that grounding methods, materials, cleanrooms and ionization play in controlling ESD and contamination in the modern cleanroom manufacturing environment. Several industry experts will share their experiences and will answer questions related to current ESD and Contamination control issues, such as selecting ESD and cleanroom safe materials, electrostatic attraction, the use of ionization and various other related topics.

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• Workshop B1. ESD Protection of High Speed / High Frequency Circuits
  Moderator: Benjamin Van Camp, Sarnoff

  At a time when the downscaling of technology makes it increasingly difficult to meet the ESD specifications, new and evermore challenging applications make the job of the ESD engineer even more complex; many traditional solutions are rejected because they introduce too much capacitance, noise, etc. The goal of this workshop is to increase the awareness and insight of the ESD designers by discussing most important figures of merit for both the ESD devices as well as the full ESD strategy, focusing on the protection of high speed interfaces. Both design and layout aspects will be discussed, comparing different protection techniques. We will compare all these trade-offs to figure out what are the remaining options in the shrinking tool box of the ESD engineer.

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• Workshop B2. Automated ESD Rule Verification & EDA Tools
  Moderator: Harald Gossner, Infineon Technology

  The manual verification of ESD protection of complex IC designs with many supply domains and voltage levels is extremely challenging and prone to flaws. Therefore many IC design companies have created in-house tools and flows for automated ESD checks. However, most of these tools focus on specific ESD checks and do not provide comprehensive ESD check functionality. Starting from a EOS/ESD Symposium workshop 2 years ago the requirements for a comprehensive automated ESD verification flow have been collected by an industry wide working group and addressed to EDA vendors. Now it's time to ask: what will be available in the near future? Which verification features should have priority in a flow implementation? How much adjustment to the company specific ESD concepts is necessary? The workshop will provide a platform for these questions and it will help you to get in touch with others working on this hot topic.

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• Workshop B3. Electrical Overstress (EOS) Failure Causes and Failure Analysis
  Moderator: Ted Dangelmayer, Dangelmayer Associates, LLC

  During this highly interactive workshop you will learn about the causes of EOS and what is known about its failure analysis. A panel of industry experts will help lead the discussion and attendees will be encouraged to actively participate. A number of common root causes will be discussed, failure analysis differentiation from ESD as well as a less well know source – ESD from Charged Board Model (CBM) stresses. How do you recognize ESD versus ESD failures? It is true that ESD from CBM is often misdiagnosed as EOS? Who is responsible for addressing EOS failures – Design or Manufacturing? What are the design protection choices for EOS protection – IC; Circuit Board and System? These are some of the questions that will be addressed during this workshop.

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• Workshop B4. Automated Equipment, ESD and Grounding Issues
  Moderator: Donn G. Bellmore, Universal Instruments Corporation

  Do you know if your Automatic Handling Equipment (AHE) and processes are capable of safely processing the latest technologies of devices with higher sensitivities to Electrostatic Discharge? Have you ever had to make voltage, field, and grounding measurements on your equipment? Have you ever had to test materials? Manufacturers constantly have to deal with a balance between cost and the ability to handle these devices in a safe and cost effective manner. This interactive workshop will focus on the grounding methods and material requirements of effective ESD Controls in AHEs in the prevention of CDM and MM type damage to ESD sensitive devices. Topics and issues for discussion are proper grounding methods, material selections, test methods, and more will be open for discussion. You are encouraged to share with the rest of the participants your issues.

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• Workshop C1. System Level Stress and the Impact on Device ESD Protection
  Moderator: Theo Smedes, NXP Semiconductors

  The IEC 61000-4-2 is a standard that specifies ESD requirements for systems, not for ICs. The system level ESD standard differs fundamentally and significantly from the component level tests. Traditionally protections against system level ESD were added on the PC as discrete devices. In the last years semiconductor manufacturers are confronted more and more by requests from customers to specify IC ESD levels according to IEC 61000-4-2. This raises the question how the IC manufacturers should deal with such ‘inappropriate’ specifications from their customers. Should such requirements be banned? Do we need to take a worst-case approach? Is it fundamentally impossible to find solutions? How should system level ESD protections be characterized? Several related studies have been published. The IEC published a technical specification for a certain class of ICs. The ESDA is writing a standard practice method, dubbing the standard as ‘Human Metal Model’. This workshop is your opportunity to learn, question, defend and challenge the system level requirements for ICs and the proposed test methods. Panelists will be available to initiate the discussion, but the workshop can only succeed with your active participation.

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• Workshop C2. TCAD for ESD
  Moderator: Michael Schenkel, Synopsys Switzerland GmbH

  The use of TCAD for ESD protection device development and optimization is state-of-the-art today. Most companies have a calibrated TCAD environment and TCAD is heavily used in process and device development. ESD teams are taking advantage of the calibrated TCAD environment to speed up ESD protection device development and gain indispensable insight not possible by measurements. However, specific know-how is required to successfully leverage TCAD for ESD. In this workshop we want to discuss advantages and limits of using TCAD for ESD protection device development. A special focus should be on the topic of ESD-specific calibration of the physical models and the model capabilities for ESD. Another point of discussion will be TCAD methodologies for ESD and how they can be integrated into the development process. Attendees are encouraged to share their experiences, possible pitfalls, and shortcomings of TCAD for ESD.

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• Workshop C3. The Challenge of CDM Testing
  Moderator: Robert Ashton, On Semiconductor

  CDM is recognized as the main ESD threat in today’s electronics manufacturing environment. Unfortunately CDM is increasingly seen as immature. There are competing standards: JEDEC and ESDA versions of Field Induced CDM (F-CDM), JEITA’s direct charging CDM and even use of the Socketed Device Model, each producing different failure thresholds. F-CDM, the most widely accepted, has numerous technical challenges. Air discharge in F-CDM has inherent variability, F-CDM is a challenge for small and odd shaped devices, the pulse size does not scale with C for large packages and waveforms that look excellent at 1GHz have higher frequency components that can affect test results. Meanwhile designers face limits on the current that can be carried during a CDM event. This workshop will allow panelists and attendees to express concerns and describe a path to a better CDM test environment.

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• Workshop C4. ESD Control and Design for Extremely Sensitive (“Class 0”) Devices
  Moderator: Steve Heymann, MKS Ion Systems

  Class 0 devices require proactive tool designs for ESD control. What are the design and control techniques required for high-yield handling and manufacturing of ALL types of highly ESD sensitive devices? How can you make sure your Class 0 device is safe? What safety margin can you afford to design into your process and tools? We will discuss considerations regarding product protection including, but not limited to semiconductor, HDD, medical devices and others. Manufacturers constantly have to deal with a balance between cost and the ability to handle these devices in a safe and cost effective manner. We will focus on techniques to protect against damage to extremely sensitive devices. Topics and issues concerning tool configuration, design practices, material selections, and test methods will be discussed in detail.

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