Friday, March 3, 2017
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Premier researcher brings to you leading edge developments in Sub-20nm CMOS Technologies brought to you by the ESDA Advanced Topics committee committed to fostering advancments in technology.
May 24 at 11:00 AM Eastern Time
ESD Reliability in Sub-20nm CMOS Technologies
Instructor: Mirko Scholz, imec
Sub-20nm CMOS technologies become mainstream. They are used to manufacture products like microprocessors, system-on-chip and system-in-package IC and FPGAs. The scaling to sub-20nm technology nodes brings major changes to the device architecture. FINFET transistors replace planar transistors due to their superb electro-static control of the channel. This results in a lower leakage and power consumption. This change in device architecture also impacts the ESD reliability. In this webinar we discusses the intrinsic ESD performance of FINFET technologies in the HBM and CDM time domain. We will show how new technology options like local interconnects impact the device behavior during ESD stress. We also cover layout optimizations for ESD diodes which are already used by some foundries in their FINFET platforms. At the end of this webinar we provide an outlook on the scaling roadmap. We discuss the ESD reliability of bulk CMOS nanowires which are one of the possible device architectures for the sub-7nm technology nodes.