ESD Design Engineer Certification 2 (EDEC2)

This certification provides courses that build upon the foundation for ESD Design Engineers to help engineers advance their skill/knowledge levels in the area of ESD device design.

The certification is comprised of 14 online courses and a knowledge assessment test for each course.

The bundled price for the certification includes all 14 required courses. There is an annual recertification required to maintain the certification.

The semiconductor industry is projected to grow from USD 452.25 billion in 2021 to USD 803.15 billion in 2028 at a CAGR of 8.6% in the 2021-2028 period. Given the large growth, this will put extreme pressure on finding quality resources and building up their technical skills so that they can be productive and knowledgeable ESD device engineers. The ESD Association (ESDA) is here to get your employees to the next level with the offering of our "new" ESD Device Engineer Certification 2 (EDEC2) program. The EDEC2 program provides takes a more comprehensive dive into the field of ESD device design.

Requirements & Cost

Registration

Initiate an official file in your name at EOS/ESD Association, Inc. headquarters. Register Online
Complete Required Minimum Prerequisite Courses

The courses are listed in the next section 'Courses'. To view course abstracts please visit https://www.esda.org/training-and-education/esda-tutorials/
Pass An In-Depth Examination

The examination is online, consisting of multiple choice questions, following each course. You are required to pass each knowledge assessment with a grade of 80% or higher.
Cost

To enroll in this program, there is an official registration filing fee and exam fee of $125. Bundle price of $2,750 for all courses.

Enterprise License Options:

Certification Program

This Certification Perpetual License grants enterprise access to all courses in the ESD Design Engineer Certification 2 (EDEC2) certification program.

Click here for more information.

Specific Course

This Certification Perpetual License grants enterprise access to a specific course from the ESD Design Engineer Certification 2.

Click here for more information.
How do I pay?

Purchase options for your organization:

Issue a Corporate PO, receive Invoice from EOS/ESD Association, Inc., execute payment

Individual Pay-complete personal purchase, receive receipt, request invoice from EOS/ESD Association, Inc., submit to company for reimbursement

Bundle PO or Invoice - Bundle multiple items for a corporate PO or purchase. Ask EOS/ESD Association, Inc. for an invoice form multiple attendees, memberships, standards, any of our products or service to process one time inside your company

Courses

Title	Runtime	Abstract	Learning Outcome
DD117: TCAD: Fundamentals and First Applications to ESD	1 hour 20 minutes	Technology computer-aided design (TCAD) tools have become an indispensable utensil for the semiconductor industry. The possibilities to analyze, predict and optimize a certain semiconductor device behavior through modeling semiconductor fabrication (process TCAD) and semiconductor device operation (device TCAD) are countless. This includes the area for ESD and latch-up development. Early access to fundamental device parameters under very high current density and high temperature transients is the key to overcoming the conceptual problem of concurrent engineering for ESD engineers. This tutorial serves as a basic introduction to the TCAD toolchain, including process and device simulation and the creation and integration of compact models for mixed more simulation. Focus points are the capabilities and limitations of these tools, like the requirements for a 2D/3D simulation approach and the validity of the models describing the fundamental physics, especially in the high-temperature regime.	On the one hand the tutorial is aimed at ESD and latch-up experts who want to clarify for themselves or their environment to what extent the use of TCAD is worthwhile in their development environment and how an introduction can be designed. On the other hand, the tutorial is interesting for students who deal with device physical effects such as high current injection and high temperature as part of their work. At the end of the course participants will have basic knowledge about the TCAD world including process and device simulation. Here the focus points are the capabilities but also limitations of these tools, like the requirements for a 2D/3D simulation approach and the validity of the models describing the fundamental physics, especially in the high temperature regime. The newly worked out second part sheds a light on selected applications allowing to understand what kind of typical ESD related questions can be addressed by such alternate development and analysis technique and what is the typical approach to get reasonable answers by the simulation tools. This part is also accompanied by a “Live-demo” that helps the interested audience to get an even more real(istic) insight into the whole tool chain and its application.
DD231: Physics, Testing, Debugging of Soft and Hard Failures	1 hour 5 minutes	The tutorial is an expanded version of the previous DD231 tutorial on system level ESD. The main difference is the addition of many experimental demonstrations, update of information, and in-depth discussion on problems of the IEC 61000-4-2 testing, with examples on how to perform this testing and obtain the best possible results and documentation. About half of the time will be spent on experimental demonstrations. Topics will include: • ESD physics: charging and discharging. • System level ESD testing • System level soft failure mechanisms and debugging • Design for avoiding ESD problems	The seminar will enable the audience to understand system-level ESD testing better. Meaningful, repeatable tests can be performed, and data is gathered to identify the root cause of observed failures. Protection of I/O using the SEED approach will be explained.
DD381/382: Electronic Design Automation (EDA) Solutions for ESD and Latch-up	45 minutes	The verification of ESD protection networks in modern integrated circuits is a difficult challenge due to increasing design and process complexity, higher-pin counts, and the overall computational difficulties in dealing with large data sets. Most chips today are segmented into multiple power domains, where ESD currents must necessarily be shunted from one domain to another, across multiple-layer interconnect paths that span major portions of the chip. Furthermore, circuit blocks that are traditionally not associated with the I/O ring and which may be far from the I/O circuits themselves, may become damaged because of the high voltages and currents produced during an ESD discharge. Relying on manual verification alone poses a significant risk of missing hidden ESD pitfalls. Consequently, automated ESD and latch-up rule checking is highly desired. An optimum verification flow should provide broad and flexible design rule coverage and allow incremental verification as a design progresses to avoid late-stage changes just before tape out. The integration of ESD checking tools into the standard design flow allows these rules to be used directly by IC designers to identify and correct most ESD issues prior to meeting with the ESD experts. This tutorial will outline the essential requirements of the ESD electronic design automation (EDA) verification flow which would be aligned within the IC design community, as discussed in the ESDA Technical Report TR18.0-01-14 (ESD Electronic Design Automation Checks). The tutorial will give an overview of existing ESD EDA solutions across industry, including both commercial and in-house EDA tools and flows for automated ESD checks and will discuss directions for future ESD EDA tool development.	After completion of this tutorial, a student should know basic ESD verification approaches. Student will become familiar with ESD EDA tools on the market and verification problems they can solve. Student will learn basic algorithms to start developing their own ESD verification decks.
DD311: Impact of Technology Scaling on ESD Devices P1	45 minutes	This advanced tutorial will focus on high-current behavior of stand-alone components, with the aim of optimizing effectiveness of ESD clamp devices (irrespectively of their schematic implementation) and maximizing the ESD SOA (Safe Operating Area). Components in both Analog and Digital technologies will be discussed, with emphasis on technology trends. This class is intended for individuals who have taken the basic on-chip protection class and are familiar with the basic device physics for both ESD and latch-up.	• Understand the physics of basic components under high current conditions with particular emphasis on scaling aspects (geometrical (i.e., W & L), power (following Wunsch-Bell power curve), and electrical (rise time). • Understand how to extract high current characteristics experimentally. • To optimize ESD protection circuits based on fundamental components behavior.
DD317: Impact of Technology Scaling on ESD Devices P2	45 minutes	Bulk FinFET has been a mainstream CMOS technology in sub-20nm nodes because of improved channel electrostatic and leakage control. ESD reliability has been investigated in bulk FinFET and is strongly impacted by newly introduced process options in the advanced technology nodes. These process options include self-align multiple patterning lithography, local interconnect (LI) defined contact scheme, and S/D epitaxial growth in different process modules. They can bring significant impacts on ESD failure level, clamping voltage and turn-on efficiency. Next to the FinFET technology, a gate-all-around (GAA) technology is a promising candidate for sub-5nm nodes. This new transistor architecture will also bring impacts on ESD device characteristics. Not only the novel transistor architectures, but new technology scaling concepts have been also proposed, for example, design-technology co-optimization (DTCO) scaling options, and system-technology-co-optimization (STCO). The corresponding influences of these future technologies on ESD reliability will also need to be further evaluated. In this tutorial, we will look at the influence of the device architectures and the corresponding technology options on ESD device characteristics in the FinFET/GAA and future technologies. Attendees will have an in-depth understanding of the ESD discharge and failure mechanism of the protection devices in advanced/future CMOS technologies.	After this tutorial, the attendees will have a clear picture of: • The corresponding process options in the state-ot-the-art FinFET and GAA technologies • How these advanced technology and process options impacting ESD device characteristics • Upcoming ESD challenges in future technology nodes
DD204: ESD Design in High Voltage Technologies	1 hour	This tutorial introduces ESD design in high voltage technologies for integrated circuits with pin voltages from 12 volts upwards. After a short introduction of typical applications and requirements, an overview of different technologies and the typical device portfolios in these technologies will be given. Different ESD protection concepts are introduced, analyzing advantages and the disadvantages of the various possible approaches to implementing ESD networks (diodes, snapback devices, active clamps, etc.). Finally, HV technology and design-related challenges regarding ESD protection are discussed, with a special focus on the formation of parasitic bipolar devices and the impact on the circuit’s ESD performance. An extensive literature list is provided for further study of various subjects regarding HV ESD.	The attendee will gain a good basic knowledge of the main characteristics of HV technologies, the different ESD protection concepts, and ESD protection challenges that are specific to HV technologies. This will be a help for understanding and further development of HV ESD protection.
EDEC2-1: Integrated Circuits Reliability for ESD Engineers	1 hour	This course provides ESD engineers with a foundational understanding of the reliability challenges faced by integrated circuits (ICs) in modern semiconductor environments. Emphasizing electrostatic discharge (ESD) and latch-up mechanisms, the course explores the impact of device scaling, material changes, and evolving technology nodes on long-term IC performance and failure modes. Engineers will gain insights into the interplay between ESD protection design and overall product reliability, with a focus on practical considerations and design trade-offs.	Upon successful completion of this course, participants will be able to: Explain the primary reliability concerns in advanced IC technologies relevant to ESD engineering. Identify how semiconductor scaling affects ESD robustness and latch-up susceptibility. Evaluate the impact of new materials and device architectures on IC reliability. Describe common failure mechanisms related to ESD, including time-dependent dielectric breakdown (TDDB), hot carrier injection (HCI), and negative bias temperature instability (NBTI). Apply knowledge of reliability testing and qualification standards (e.g., JEDEC, AEC-Q100) in ESD protection planning. Understand the relationship between ESD protection design and overall product lifetime and performance. Recognize the limitations and considerations of integrating ESD structures in advanced CMOS technologies.
DD300: Circuit-level Modeling and Simulation of On-Chip ESD Protection	1 hour 30 minutes	This tutorial addresses modeling of on-chip ESD protection devices and simulation of ESD protection networks. The primary focus is SPICE-type simulation with compact (physics-based) models but a brief survey of other modeling approaches and simulation techniques will be provided. The physical operating principles of commonly-used ESD protection devices will be examined. The high-current characteristics and transient responses of those devices will be explored to ascertain what behaviors should be captured by a model intended for circuit-level simulation of ESD. Specific examples of model implementations will be provided. Techniques for circuit-level modeling of self-heating will be presented. Parameter extraction and model scalability will be addressed. This tutorial assumes some familiarity with device physics. It is directed toward persons with interests in semiconductor device physics, electronic design automation, and on-chip ESD protection circuit design.	After completing this tutorial, a student should know how to set up a netlist to simulate an on-chip ESD protection network. Students will have the necessary background to start developing compact models and be familiar with Verilog-A model development resources.
DD201: ESD Protection and I/O Design	1 hour 45 minutes	This tutorial is intended to provide the attendees with the tools to take a device and circuit level understanding of ESD protection methods and implement them effectively in I/O designs for CMOS bulk technologies. Beginning with a review of common ESD protection strategies, this course will focus more directly on how to build ESD-robust I/O cells and how to integrate them on a full chip. The tutorial will cover various types of I/O pads including analog, RF and digital pads. Different types of ESD protection strategies and their usage in I/O pad cells will be described, for example rail clamp, self-contained, and SCR based protection schemes. This course will also discuss the decisions and challenges which ESD and I/O designers typically face when designing I/O pads. More complex ESD solutions will also be described such as stacked rail clamps, ghost rails, and protecting signals that can swing below ground or above the supply. Finally, this tutorial will touch on various supply schemes including multiple power domains and isolated grounding schemes. It will end with discussing pad ring construction aspects for both wire-bond and flip-chip packages.	• Understand devices commonly used for ESD protection in CMOS bulk technologies. • Implement and verify circuit-level ESD protection in I/O designs. • Build pad cells needed for complete I/O libraries. • Construct I/O pad rings. • Address unique ESD, I/O cell, and pad ring issues.
DD150: Introduction to RF ESD Design	1 hour	This tutorial is an introduction to RF concepts and RF ESD clamp design. It is intended for ESD engineers who do not have an RF background to learn the concepts needed to design effective protection circuits. The RF concepts include impedance matching and smith chart basics. RF amplifier operation and load line basics are presented to give a foundation for the RF ESD protection circuit design. The tutorial will also touch briefly on RF switches and filters. The second half of the tutorial will focus on designing an ESD clamp for an RF application. Concepts will be presented, such as calculating the turn-on voltage of the clamp such that it will protect the part but not turn on during normal, RF operation. A clamp’s parasitics also need to be considered in an RF application so that the parasitics do not degrade the product’s performance. Finally, some testing tools will be reviewed concerning testing RF products. The challenges will be highlighted, and different testing practices that are used in HBM, TLP, and IEC testing of RF products will be reviewed.	This tutorial is aimed toward those individuals who need to design ESD protection circuits for RF and millimeter wave applications. After completion of this tutorial, a participant will understand the fundamental RF concepts critical to designing RF ESD on-chip protection schemes. The participant will gain a basic understanding of how RF components such as amplifiers, switches, and LNA’s performance metrics will impact the design of ESD clamps and why traditional digital and CMOS ESD clamps can degrade RF performance. Finally, individuals who take this tutorial will know how to design ESD clamps with components such as HBTs and PHEMTs for Gallium Arsenide (GaAs) and MOSFETs for Silicon-on-Insulator (SOI).
DD340: ESD System Level Simulation	1 hour	The tutorial is a hands-on training course for performing a simulation based optimization of PCB ESD protection design and provides deep understanding of the relevant performance criteria both of TVS diodes and IO circuits. The presented method follows the system efficient ESD design (SEED) approach as recommended by the Industry Council on Target Levels and JEDEC. The method allows the achievement of correct first time PCB builds and reduces the respin effort for boards and ICs. Based on a TLP characterization of SoC interface circuits and TVS diodes, simulation models for impedance and clamping behavior, as well as failure threshold, are extracted. These are used to assess design solutions by transient simulations. This is showcased by real world examples.	The attendee will understand the concept of SEED simulation and will be able to apply it to an own PCB /IC codesign simulation. This will allow the system design attendee to run a pre-hardware optimization of the board protection and it will enable the IC protection engineer to evaluate his protection concept regarding the available design window for system ESD
DD200: Charged Device Model Phenomena, Design, and Modeling	2 hours	This course teaches basic ESD circuit design concepts and ideas required to design ESD protection for Charge Device Model ESD tests. The course covers a brief history of CDM ESD development, charge and discharge physics, characterization methods, CDM failures mechanisms, and CDM design-in strategies. CDM ESD circuit design approaches and simulation setups for CDM failure debugging are presented in this tutorial on the basis of case studies. Insight into CDM circuit simulation requirements and physical aspects of the CDM ESD phenomenon that are important for reproducing the event with circuit simulation will be taught and modeling approaches for CDM specific device physical effects necessary for accurate circuit simulation will be introduced. This curse also teaches methods for simplified CDM circuit simulations where detailed information is either not available or too complex to simulate. The course focuses on what type of circuits fail during a CDM discharge event and teaches the different types of ESD design circuit strategies that can be applied to protect those circuits. This class covers basic to advanced topics for CDM ESD design, but the student is assumed to already have a basic understanding of the CDM test method.	The attendees of this class are expected to have an improved understanding of the basics of charging of an IC component, CDM discharge event physical effects, internal circuit damages caused by the voltage and current during fast transient discharges, and basic high current properties of ESD protection circuits in the CDM time domain. They should have an improved appreciation of circuit simulation methods for designing CDM ESD protection and debugging failures caused by CDM ESD with circuit simulations. They should be able to apply ESD design strategies as discussed in the tutorial that has proven to protect ultra-thin gate oxides of input circuitry and of devices connecting to signals that cross power domains techniques and strategies to protect cross-domain circuits.
DD214: Latchup Physics and Prevention	1 hour	Latchup has occurred in CMOS technologies since their inception and continues as a threat in modern finFET technologies. This course will begin with a basic overview of the latchup phenomenon and then dig deeper into the theory and physics associated with it. Latchup mitigation techniques will be reviewed along with the physics behind them. These will include both design and process techniques. The basics and pitfalls of latchup testing will be taught, along with an introduction into transient latchup. Proper wafer-level test structure design and characterization will be taught. The primary audience for this course is design and reliability engineers tasked with designing for latchup success. Latchup test engineers will also benefit from a deeper understanding of latchup physics and design practices. The course assumes some familiarity with basic circuit design practices and semiconductor physics. Participants will leave with a deeper understanding of the physics behind latchup, its mitigation, and the impact of future technology trends on latchup susceptibility.	• Understand the physics behind latch-up • Understand how technology scaling impacts latch-up • Learn latch-up mitigation strategies in design and process development and the physics behind them. • Will learn best practices for test structure creation and measurement and how to translate the results into latch-up design rules. • Will understand the latch-up test standard in the context of creating design rules to successfully pass the test as well as other real-world risks not covered by the standard
DD302: Trouble-shooting on-chip ESD failures	1 hour 40 minutes	Diagnosing and fixing on-chip ESD product qualification failures can often be one of the more challenging aspects of ESD work. The pressure to quickly find and correct an HBM/MM/CDM failure to qualify a product often compounds the inherent difficulty of troubleshooting. Experience diagnosing failures, though not desirable from a product qualification standpoint, greatly improves troubleshooting skills. This tutorial will build troubleshooting experience and skills by presenting case studies of actual on-chip HBM failures in a workshop format. The evidence for each case will be revealed, and the failure analyzed in the same manner as an actual failure. Participants will be led through and allowed to analyze each failure case, interacting with the instructor to determine its root cause and a solution. This tutorial will identify common concepts, methods, and tools useful in failure diagnosis. Participants should be familiar with CMOS technology, on-chip ESD breakdown phenomena, standard ESD protection circuits, and the HBM test procedure. Participants should also be acquainted with basic CMOS circuit design, should be able to read circuit diagrams, and should have a basic understanding of the function of IO circuits.	After completing this course, the student will be able to conduct Troubleshooting of On-Chip ESD Failures in a disciplined, results driven methodology. The student will have gained practical experience troubleshooting real-world failures and will understand many nuances of device behavior that cause an On-Chip ESD implementation to behave in an unintended way.

Continuing Education & Renewal

Continuing Education & Renewal

To maintain certification, an annual renewal fee of $150 is required, along with the completion of 3 credits of ESDA Online Academy Design-Related Course. Alternatively, provide evidence of completing 3 hours of ESD Design-related instruction from another provider within the past 12 months.

How To Register