ESD Design Engineer Certification (EDEC)

Title

Run Time

Abstract

Learning Outcome

An Overview of Integrated Circuit ESD:The ESD Threat, Testing, Design Concepts and Debugging DD103

2 hours

This three hour tutorial is focused on integrated circuit ESD fundamentals, and is targeted for two audiences: the IC circuit designer who needs knowledge of how ESD can affect IC design, test, handling and system use; and those engineers wishing to be introduced to IC ESD, as a primer to further study.
The tutorial covers the following topics:
• ESD Definitions
• Overview of the ESD Threat and ESD Controlled Workspaces
• ESD Stress Models and Standards
• Introduction to Transmission Line Pulse (TLP) ESD Testing
• ESD Design Window
• ESD Protection Network Design
• Power Clamp ESD Design and Tradeoffs
• Input Protection ESD Design
• Output Drivers ESD Design
• Switches (Transmission Gates) ESD Design
• RF ESD Protection
• IC ESD - Integration Issues
• CDM Protection Guidelines
• ESD Design Verification
• ESD Debug and Diagnosis

Upon completion of the tutorial, the student will have a basic understanding and impact of
• The ESD Threat to ICs and ESD Controlled Workspaces
• Device Level ESD Stress Models and Standards
• Transmission Line Pulse (TLP) ESD Testing
• ESD Design Window – proper region of operation for an ESD device
• Protection – Network Design, Power Clamps, Input / Output / Switch Protection
• RF ESD Protection Concepts
• ESD Element Whole Chip Integration Issues
• CDM ESD IC Protection Guidelines
• ESD Simulation and Design Verification Concepts
• ESD Failure Diagnosis and Failure Analysis Methods

ESD Basics to Advanced Protection Design DD110

2 hours 5 minutes

This course gives a comprehensive overview from ESD basics to ESD on-chip design principles, covering up to the latest silicon technologies appealing to a variety of engineers from design to process technology, and failure analysis to quality. The attendee will have an in-depth understanding of the principles of ESD device design along with a full perception of what it takes to address almost every kind of design scenario, how to apply rules of thumb for successful on-chip design, knowledge of lessons learned from case studies, and empowerment to communicate with customers on ESD quality issues. In its complete ESD overview, the course offers emphasis on on-chip protection methods including an under­standing of any interactions to the eventual system protection.

This course uniquely provides a complete picture of the ESD phenomena from A to Z, from component to system ESD issues. It is specifically aimed at beginning ESD designers to become familiar with the basics of ESD design parameters and ESD physics. It should be also attractive to those who already have some knowledge but wish to expand it by learning about some of the advanced designs and various protection schemes for different applications such as low voltage CMOS and high voltage analog. After taking this class the ESD designer should be able to choose the proper protection option and estimate its performance to meet the target ESD levels.

Human Body Model Testing Essentials DT100

1 hour

This tutorial addresses the details of human body model (HBM) qualification testing. This course will help in the interpretation of the HBM joint standard JEDEC/ANSI/ESDA JS-001 and will include details on waveform verification, understanding of Table 2A (minimum required set of pin combinations) and Table 2B (legacy pin combinations), pin categorization and pin grouping, and I/O pin sampling. Stress plan details will be discussed including efficient testing (reduction in pin count) and some debugging options.

• Build a stronger understanding of the human body model (ANSI/ESDA/JEDEC JS-001 - HBM) testing specification and the requirements within.
• Understand the differences between Table 2A and Table 2B and the use of associations in Table 2A for HBM testing.
• Understand opportunities to minimize test time, and cloned IO requirements in HBM testing.

CDM Testing Essentials DT200

45 minutes

This tutorial will give students the fundamental information required to quickly learn the CDM testing method on commercial CDM test equipment and the associated oscilloscope/metrology chain information needed to capture and interpret CDM waveforms. Additional information on CDM testing standards and their hardware differences, package effects on the CDM waveforms, and package limitations will be covered. Students will also be introduced to the background information needed in understanding CDM failure modes along with test program output failure types needed to understand the effects of CDM testing.

The student should have the following learning outcomes from this course:

• Understanding of how CDM ESD Testing compares to HBM (Human Body Model) ESD testing
• How CDM and CDM testing developed in the electronics industry
• Understand similarities and differences between different industry CDM test standards, as well as between contact and field-induced CDM
• Understand the test hardware setup for the field-induced CDM tester
• How to describe field-induced CDM tester discharge current waveforms
• Acquire a basic understanding of how CDM discharge current waveform is affected by the IC package
• Understand the reasoning and need for CDM tester qualification / waveform verification
• Understand the CDM test procedure – part requirements / pin stressing / voltage test levels
• Understand how to setup an oscilloscope for CDM waveform verification / calibration
• Acquire basic understanding of IC CDM failure modes in circuits – CDM test diagnosis of failures

Latch-Up Testing and Troubleshooting DT201

45 minutes

This tutorial focuses on latch-up testing and troubleshooting. Latch-up is a failure mechanism primarily seen in CMOS and BiCMOS technologies but can be present in bipolar technologies. During process development, resistance to latch-up is generally characterized and design rules are implemented at device circuit block layout. Design checks for latch-up are often implemented, but latch-up immunity is generally guaranteed by testing. This tutorial will help the student understand the issues related to latch-up testing, ways to prevent latch-up and methods used to verify latch-up resistance in products using the Latch-up Standard, JESD78, test method.

Students will learn how to
• Understand how a latch-up event can occur
• Evaluate the possible latch-up sensitivity as it relates to design rules
• Understand how the JEDEC Latch-up standard has evolved
• Apply the JEDEC Latch-up standard and the nuances that must be considered
• By using examples of actual test set-ups, demonstrate the application of the Latch-up standard and helping understand the nuances of the testing

Fundamentals of Failure Analysis DT142

1 hour 45 minutes

Failure analysis is the diagnostic tool of the semiconductor industry. It is the semiconductor equivalent of forensic science. Failure analysis unravels the mystery behind how and why a part failed, determining the root cause and corrective actions needed to prevent future failures. This tutorial is targeted toward people doing stress testing on a daily basis where failures are generated and need to be analyzed to determine what failed and how to improve a part’s robustness. The focus will be on failure analysis methods and tools used to analyze failures resulting from ESD, TLP, or latchup related stressing but will be applicable for wear out as well as infant mortality-related failures as well. The tutorial will cover the five basic steps necessary to perform a failure analysis:
1) Information Gathering,
2) Failure Verification,
3) Failure Site Localization,
4) Root Cause Investigation, and
5) Corrective Action.

• Understand the purpose of failure analysis and the electrical signatures of ESD/Latch-up  failures
• Obtain an general overview of the failure analysis flow highlighting the key steps and sequence followed that yields a successful conclusion and corrective action
• Understand the use of key tools and techniques to perform failure analysis
• Understand the key failure mechanisms caused by ESD and Latchup

TLP Fundamentals – Understanding the Equipment Options DT210

45 minutes

This tutorial explains what transmission line pulsing (TLP) is and how it can be used for ESD design and development. Taking accurate TLP measurements is important; thus, how TLP systems make measurements and produce IV plots will be reviewed. The IV plots provide very valuable device parameters that are key to understanding the DUT being stressed. The tutorial also explains the parameters extracted from those IV curves. Finally, typical equipment used in TLP systems is reviewed.The tutorial will also explain the parameters that can be extracted from those IV curves. Finally, typical equipment used in TLP systems will be reviewed.

• Understand how TLP pulses are generated and delivered
• Understand reflections in transmission lines
• Learn how TLP I-V curves are constructed and the major points that they show
• Learn about load lines and how changes in TLP impedance changes the I-V curves
• Will learn the difference between TLP and VF-TLP 
• Will understand the correction and calibration steps for accurate TLP measurements

Fundamentals of ESD System Level DD134

1 hour 10 minutes

This tutorial is intended to help those tasked with designing and testing prod-ucts to system-level ESD standards by providing first an overview of what the real-world system ESD threats are and the associated standards that describe these events. Then detailed information on qualification testing is given on IEC 61000-4-2, the most widely used standard, but also ISO 10605 and other standards. This topic includes waveform verification, discharge points, test levels and result classification. System level characterization is broken into five different types including, testing of components outside a system, cable discharge events, charge board events, electro-magnetic field scanning and SEED – system efficient ESD design. The last part of the course dives into the design and simulation strategies for system level robustness where on-board and on-chip protection need to work together. The more popular components for on-board protection are presented and compared.

After attending this tutorial one will understand the differences between the types of ESD events that occur during IC handling and assembly, board subassembly testing, and final system level operation. One will understand what the similarities and differences of on-board protection and on-chip protection are and how these need to work together to achieve system level robustness. Finally, one should be able to understand the overall design and characterization approaches to be able to create a robust system level solution for their products.