EOS/ESD Association, Inc.

Setting the Global Standards for Static Control!

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Discussion/Special Interest Groups Co-Chairs:

Tom Meuse, Thermo Fisher Scientific tom.meuse@thermofisher.com
Eugene Worley, Qualcomm, Inc. eworley@qti.qualcomm.com

The evening discussion groups are an integral part of the workshop. Two parallel discussion groups are offered each evening Monday through Wednesday. Each discussion group has one or more moderators with extensive expertise on the topic to help guide and inspire the discussion. The success of these sessions depends on your active participation. We encourage you to bring along data, ideas and other items of interest to share. Contacting session moderators with questions, comments or suggestions prior to the event is also encouraged. As the workshop approaches, please check the IEW web site for updates from the discussion group moderators. Interested in forming a new Special Interest Group (SIGs), focused on one compelling topic of mutual interest? Please contact Tom Meuse and Gene Worley for SIG creation details.

Discussion Groups Session A
Parallel Groups-Monday 7:10-8:30 PM

DG A.1 Inter Chip ESD design in 3D ICs

Moderator: Souvick Mitra, GLOBALFOUNDRIES, souvick.mitra@globalfoundries.com

For chip to chip signaling in 3D IC’s it is highly desiable with respect to speed and power to use low voltage MOSFETs for the I/O’s. For the sake of area and loading, the ESD protection should be as small as possible. But how small? Whereas the package level tests and specs are well definfed, 3D die assembly ESD tests are not defined at all. Nothing is kown about the discharge waveform. Should a JEDEC/ESDA committee be formed to develop a test methodology and corresponding spec?

DG A.2 CDM Testing

Moderator: Tom Meuse, Thermo Fisher Scientific, tom.meuse@thermofisher.com

With RF frequencies going up, faster SERDES ports, and extreme technology scaling, is it time to lower the CDM recommendation to 125 volts? Can factory ESD control equipment handle the job and at what cost? Also, what can be done to make low voltage disharges on CDM equipment less erratic? Contact methods are being investigated as a way of improving the test method, will contact CDM help define new factory levels or set new standards? 

Discussion Groups Session B
Parallel Groups-Tuesday 7:10-8:30 PM

DG B.1 Survival and Reliability Issues of the Auto Industry

Moderator: John Mason, General Motors, john.3.mason@gm.com

How does the automotive industy deal with EOS? How does the industry prioritize EOS and reliability failures? What are the typical failure modes and can anything be done to improve it? Are high temperature effects and high noise of the auto environment responsible for EOS failure? Do you design specifically for the auto industry or do you use a generic design and package and test to auto industry standards?

DG B.2 IEC Testing

Moderator: Hans Kunz, Texas Instruments, Inc. hkunz@ti.com

The IEC spec has issues as it relates to the real world and how to properly design a circuit for it. To begin with, contact discharge does not occur in the real world, but yet is specified for exposed metal surfaces. For air discharges, the initial spike is muted and, therefore, not much of a design issue but for contact discharge it can be.  Is the HCP to ground plate capacitance 60 pF as found in one paper or 120 pF in another? Some advocate connecting the gun ground strap directly to the HCP for automotive applications.  How are discharges introduced into connector signals where the connector has a robust ground shield? Likely direct pin discharges or through cables? Are HMM testers useful for design evaluation and where are they applied?

Discussion Groups Session C 
Parallel Groups-Wednesday 7:10-8:30 PM


Moderators: Harald Gossner, Intel, harald.gossner@intel.com; Jeff Dunnihoo, Pragma Design, jeffhoo@pragma-design.com

As technology continues to downscale, SOC’s driving external ports and the lowering of the HBM spec (from 2 kV to 1 kA and even lower in the future) can translate into I/O’s where there are no TVS system level clamps that can protect them. Adding to the mix is the loading of TVS devices on high speed SERDES ports; not to mention the ambiguities of the IEC 61000-4-2 test. Whereas in the past, the I/O designer didn’t have to worry about interfacting to TVS clamps and passing an IEC spec, now he does. This session asks what does the desinger need to do to make sure his I/O’s can sucessfully interface to a TVS clmap to meet an IEC spec.

DG C.2 Absolute Maximum Rating (AMR)

Moderator: Alan Righter, Analog Devices, alan.righter@analog.com

AMR is defined as the maximum voltage that may be applied to a device, beyond which damage (latent or otherwise) may occur according to JEDEC. Absent in the definition are temperature, current, failiure-In-time (FIT). Should there be a more precise difinition of AMR or leave it up to manufacturers to define the AMR of their products? Are there any industry specific definitions such as for the automobile industry?