EOS/ESD Association, Inc.

Setting the Global Standards for Static Control!

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IEW Schedule

Sunday, May 7, 2017

1:30 PM-4:00 PM 

Registration: Pick up badges and handouts.

4:00 PM-4:30 PM

Hotel check-in: Get room assignment & room key.

12:00 PM-1:30 PM

Lunch

1:30 PM-4:30 PM

Free Time

4:30 PM-6:00 PM

Hosted Reception

6:00 PM-7:30 PM

Dinner

7:30 PM-8:30 PM

Welcome/Entertainment

8:30 PM-9:30 PM

Networking/Social Gathering

Monday, May 8, 2017 

7:30 AM-9:00 AM

Breakfast

9:00 AM-9:30 AM

Welcome

9:30 AM-10:40 AM 

Keynote: Emerging Interconnect Technologies for Nanoelectronics
Krishna Saraswat, Department of Electrical Engineering, Stanford University

10:40 AM-11:05 AM

Break

11:05 AM-12:05 PM

 

Seminar 1: ESD in 3D IC: Challenges, Standards, and Design Requirements
James Karp, Xilinx Inc

12:05 PM-1:35 PM

Lunch

1:35 PM-2:35 PM

Invited Talk 1: TBD

2:35 PM-3:20 PM

 

Technical Session A:

A.1 Skin-Depth Losses in Measurement Cables and Their Effect on CDM Waveforms
Timothy J. Maloney, Intel

A.2 Methodology  to Enhance ESD Performance of Fullysalicide 5V MOSFET in Submicron CMOS
Krishna Mohan Chavali, GLOBALFOUNDRIES

A.3 TCAD Study on Electron Collection Efficiency during Latch-up Test
Yunfeng Xi, Michael G. Khazhinsky, Jeremy C. Smith
Silicon Laboratories

A.4 Update on JS-002:  Component Results Compared to other Standards and Test Standards Harmonization
Alan Righter, Analog Devices

A.5 Premature FDSOI Device Failure in Wafer-level HBM Testing
Alain Loiseau, Richard Poro, Manjunatha Prabhu, Robert Gauthier, GLOBALFOUNDRIES

A.6 Measurement Capacitance of Small Packages to CDM Field Plate
Robert Ashton, ON Semiconductor 

3:20 PM-4:35 PM 

Poster Discussion Session A

4:35 PM-5:00 PM

Break

5:00 PM-6:00 PM

Invited Talk 2: ESD Waveform Capture
Elyse Rosenbaum, University of Illinois at Urbana-Champaign

6:00 PM-7:10 PM

Dinner

7:10 PM-8:30 PM

Discussion Group Session A: Parallel Groups 
DG A.1 - Inter Chip ESD design in 3D ICs
DG A.2 - CDM Testing

8:30 PM-9:30 PM

Networking/Social Gathering

Tuesday, May 9, 2017

7:30 AM-9:00 AM

Breakfast

9:00 AM-9:10 AM

Announcements

9:10 AM-10:10 AM

Invited Talk 3: Cognitive Applications Platform: (Artificial) Intelligence at the Edge
Jim Hogan, Vista Ventures, LLC

10:10 AM-10:20 AM

Break

10:20 AM-11:20 AM

 

Invited Talk 4: A Perspective on Heterogeneous Integrated Edge Devices for Internet of Things
Dr. G. P. Li, University of California, Irvine

11:20 AM-12:00 PM

Report on DG Sessions A

12:00 PM-1:30 PM

Lunch

1:30 PM-6:00 PM

Open Time

6:00 PM-7:10 PM

Dinner

7:10 PM-8:30 PM

Discussion Group Session B: Parallel Groups
DG B.1 - Survival and Reliability Issues of the Auto Industry
DG B.2 - IEC Testing

8:30 PM-9:30 PM

Networking/Social Gathering

Wednesday, May 10, 2017 

7:30 AM-9:00 AM

Breakfast

9:00 AM-9:10 AM

Announcements

9:10 AM-10:10 AM

 

Seminar 2: EOS from A to Z – The Pursuit of Analyzing, Reproducing, and Preventing EOS Failures with Zeal
Scott Ward, Texas Instruments

10:10 AM-10:20 AM 

Break

10:20 AM-11:20 AM 

Invited Talk 5: ESD Compact Models and their Applications
Michael "Michi" Stockinger, NXP Semiconductors

11:20 AM-12:00 PM

Report on DG Sessions B

12:00 PM-1:30 PM

Lunch

1:30 PM-2:30 PM

Seminar 3: ESD Control in Manufacturing:  Techniques, Programs and Challenges
Terry Welsher, Dangelmayer Associates, LLC 

2:30 PM-3:00 PM 

Picture / Break

   

3:00 PM-3:45 PM

 

Technical Session B:

B.1 Advanced Behavior Modeling of ICs for System-ESD Simulation with Destruction Limits in SPICE
Michael Ammer, Infineon Technologies AG, Universität der Bundeswehr; Kai Esmark, Andreas Rupp, Friedrich zur Nieden, Yiqun Cao, Infineon Technologies AG; Martin Sauter, Linus Maurer, Universität der Bundeswehr

B.2 System Level ESD Design Challenges for Emerging Mobile Markets
Yupeng Chen, Umesh Sharma, ON Semiconductor

B.3 Electrostatic Discharge (ESD) Effects on Wireless Power Transfer Using Magnetic Resonance Coupling
Sukjin Kim, Han-Gu Kim, System LSI Businessm Samsung Electronics, Ltd.; Yeonje Cho, Joungho Kim, Terahertz Interconnection and Package Laboratory, EE, Korea Advanced Institute of Science and Technology (KAIST)

B.4 Device Compact Modeling for System Level ESD and EMC Simulation
Yuanzhong (Paul) Zhou, Analog Devices

B.5 ESD Protection Circuit Design for 30GHz HSS and Beyond in Advanced FinFET
Manjunatha Prabhu, Brian Hulse, Suresh C, Anand K, You Li, Robert G., Globalfoundries

B.6 Don‘t be "Strung" Along by EOS
Dorothy Taylor, Texas Instruments 

3:45 PM-5:00 PM

Poster Discussion Session B

5:00 PM-6:00 PM

Seminar 4: Extending SEED Concept to Soft Fails
Harald Gossner, Intel Corporation

6:00 PM-7:10 PM 

Dinner

7:10 PM-8:30 PM

 

Discussion Group Session C: Parallel Groups
DG C.1 - SEED
DG C.2 - Absolute Maximum Rating (AMR)

8:30 PM-9:30 PM

Hosted Reception

Thursday, May 11, 2017 

7:30 AM-9:00 AM

Breakfast

9:00 AM-9:10 AM

Announcements

9:10 AM-9:40 AM 

Industry Council Report

9:40 AM-10:20 PM

Report on DG Sessions C

10:20 AM-10:35 AM 

2018 Announcements and Closing

By 11:00 AM

Hotel Check-Out