Overview on ESD and Latch-up Challenges in 2.5D and 3D-Stacked ICs & ESD Design Challenges of RF and High Speed I/Os

Overview on ESD and Latch-up Challenges in 2.5D and 3D-Stacked ICs & ESD Design Challenges of RF and High Speed I/Os

$450.00

2.5D and 3D integration are commercially available packaging options in the semiconductor industry. The Industry Council on ESD targets level is working on a white paper that discusses the ESD challenges of die-to-die interfaces in 2.5D/3D stacked ICs. In this invited talk, we provide an overview of the ESD and latch-up challenges that are currently solved or need to be solved in the near future. We discuss the impact of 3D integration on the ESD and latch-up robustness. ESD testing challenges like the assessment of the CDM robustness of internal IOs are covered and the specific requirements for the ESD protection design in 2.5D/3D stacked ICs are discussed. Our talk will show that all ingredients for the successful enablement of commercial 2.5D/3D stacked ICs are ready to be used.

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