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Device Design Certified Professionals

The ESD Association is pleased to award  Professional Device Design Certification  to the following individuals. (In alphabetical order)

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Rosario Consiglio

Certified 2007  

One of Silicon Valley’s most prolific ESD device and design professionals, Rosario has completed more than 3,700 ESD design applications and 43 device libraries while at Advanced Micro Devices, LSI Logic, Maxim, VLSI Technology, and Impulse Semiconductor. Founded by Rosario in 1994, Impulse Semiconductor Inc. is an ESD metrology, design, and troubleshooting engineering service organization.

With more than 20 years of experience in the field, he is an expert in product applications involving on-chip protection for human body model (HBM), machine model (MM), and charged device model (CDM) ESD, to include European IEC specifications.

A graduate of Marquette University Electrical Engineering, Rosario has 11 patents covering ESD technology, from transmission line pulser instrumentation to semiconductor devices and circuits.  

Rosario is also a bass fishing enthusiast, enjoys playing ice hockey, and watching Green Bay Packer football.




Charles Meyerson

Certified 2009    

Charles Meyerson received his B.S. and M.S. in Electrical Engineering from Arizona State University in 1987 and 1997, respectively. He has been employed at the Medtronic Microelectronics Center in Tempe, Arizona from 1987 until present. After two years as an IC test engineer, Charles has worked the last 20 years as an IC design engineer. He has worked as both a digital and analog designer and as chip lead. Charles maintains strong interests in both design for test and design for reliability and has been actively involved in the use of IEEE 1149.1 and 1149.4 boundary scan standards. For the past several years, Charles has worked as an ESD and IO cell designer with responsibility for ESD device design, IO cell libraries, pad ring design and ESD failure analysis.




Warren Anderson


Warren Anderson is currently a Principal Member of the Technical Staff at AMD, where he leads a team designing I/O and ESD circuits for AMD’s microprocessors.  Prior to joining AMD, he worked on I/O technologies at Intel, and also worked for Hewlett Packard and Compaq Computer, where he designed ESD protection and led an I/O design team.  After receiving his Ph.D. in applied physics from Yale University, he worked at Digital Equipment Corporation, focusing on ESD protection design, latchup, and soft error upset.           Warren’s areas of expertise include I/O circuit design, I/O jitter modeling and performance prediction, ESD protection, and signal integrity.  His publications include numerous papers on ESD protection design, as well as, contributions to three books. He has delivered lectures on ESD and I/O circuit design through the University of California Berkeley Extension and the ESD Symposium tutorials.  He holds 10 patents on ESD protection devices, circuits, and I/O design techniques.


Robert Ashton


Robert Ashton


Robert Ashton is a Senior Protection & Compliance Specialist in the Discrete Products Division at ON Semiconductor in Phoenix, Arizona. He has authored or co-authored numerous papers on ESD, test structure use in integrated circuit development, and CMOS technology. He is active in ESD and EOS standards development with ESDA, JEDEC, and IEEE SPDC. He is ON Semiconductor’s representative to the Industry Council on ESD Target Levels.
Previously, Dr. Ashton served as Director of Technology at White Mountain Labs (now a part of Evans Analytical Group), a provider of ESD and latch-up testing of integrated circuits, and he was a Distinguished Member of Technical Staff at Agere Systems, Bell Labs Lucent Technology, and AT&T Bell Labs, in integrated circuit technology development. He received the B.S. and Ph.D. degrees in Physics from the University of Rhode Island and held post doctoral positions at Rutgers University and Ohio State University.




Gianluca Boselli

Gianluca Boselli completed his Masters in E.E. at the University of Parma, Italy, in 1996. In 2001, he completed his Ph.D. at the University of Twente, The Netherlands. 

In 2001, he joined Texas Instruments, Dallas, Texas, where he focused on ESD and Latch-up development for advanced CMOS technologies. Recently, his responsibilities extended into ESD development of Analog technologies.

He authored several papers in the area of ESD and Latch-up. He presented his work at major conferences, including EOS/ESD Symposium, IEDM, and IRPS. He also presented several invited papers and/or tutorials at the EOS/ESD Symposium, IRPS, IEDM, ESREF, and RCJ.

Dr. Boselli has been the recipient of the “Best Paper Award” on behalf of Microelectronics Reliability Journal in 2000. He received “The Best Paper Award” at the EOS/ESD Symposium in 2002. He also received the “The Best Presentation Award” at the EOS/ESD Symposium in 2002 and in 2006.


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Michael Chaine


Mike Chaine works at Micron Technology, Inc., in Boise, Idaho, as a Section Manager in the R&D Reliability Group. He has a B.S.E.E. degree from Arizona State University and has worked at Micron since 1998. Today, he is leading the R&D Reliability Group in the area of ESD/LUP design and development, and has two engineers reporting to him. He is working in the area of On-Chip ESD protection design for all advanced DRAM and FLASH technologies. These responsibilities include ESD wafer and device level characterization analysis, ESD circuit failure analysis, and ESD design and layout rule development.

Mike has authored several papers on a variety of ESD areas ranging from ESD device test issues, ESD protection circuit analysis, and unique ESD circuit interaction phenomena. He holds more than 10 ESD patents and has several patents pending.

Mike chairs two different IC device work groups; Human Body Model (HBM) WG5.1 and Socketed Device Model (SDM) WG5.3.2.


 Charvaka Duvvury

Charvaka Duvvury


Charvaka Duvvury received his Ph.D. in Engineering Science and worked as a Post-Doctoral Fellow in Physics. He is a Texas Instruments Fellow working in the External Development and Manufacturing Group. His current work is on the development and company wide support of ESD for the nanometer submicron CMOS technologies. Charvaka has made numerous international presentations on ESD phenomena and on-chip protection design. He has published over 130 papers in technical journals and conferences,  holds 64 patents, and has co-authored 3 books.  He is a recipient of the Outstanding Contributions Award from the ESD Symposium (1990) and numerous Best Paper/Best Presentation awards from the ESD Symposium.  Charvaka served as the General Chairman of the ESD Symposium both in 1994 and in 2005. He has been a member of the ESD Association Board of Directors since 1997, promoting university education and research in ESD. Charvaka is also a Fellow of the IEEE.



Leo G. Henry, Ph.D


Leo G. Henry is presently an ESD Consulting Engineer.  He has worked in the electronics industry for over 25 years and in the field of EOS and ESD for over 19 years.  Over the years, Leo G. has worked in several engineering capacities for several companies (ORYX, BEI, ION, GTL, EPI), and spent over 14 years at Advanced Micro Devices (AMD) as a Member of the Engineering Technical Staff (MTS).
Leo G. received his B.Sc. and M.Sc. degrees in Physics from the University of the West Indies.  He received his M.S. and Ph.D. degrees in Materials Science & Engineering at the University of California at Berkeley, USA.

Dr. Henry has taught Physics, Materials Science, and Failure Analysis (FA) Principles at SJS University, and ESD at various conferences and symposiums from 1997-2008.  He has also presented at conferences and published many papers on ESD, EOS, TLP, FA, and Materials Science.  His technical expertise also includes system level testing using the IEC ESD standard.  

Dr. Henry is a senior member of the IEEE, a member of ASM/EDFAS, and BoD member of SiVa. Leo G. is presently overall chair of the ESD Association's ESD Device Testing Standards Working Group 5.0, and chair of the MM 5.2 WG. He has served on the ESDA's TPC (1996-2006), as National Tutorial Program (NTP) chair (2003-2006), and is a member of the Association's Technical Advisory and Support (TAS) committee for Standards.   As an elected member (1995-2000 & 2002-2008) of the Board of Directors of the ESDA, he is part of the industry liaison team, and is presently the Jr. Vice President of the ESDA Association, with overall responsibility for Education, Symposium, Standards, and ESD Facility Certification.  Leo G. teaches classes associated with the Pr.M and D.D certification programs.



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Steven H. Voldman

Dr. Steven H. Voldman is the first IEEE Fellow for “Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology” and recipient of the ESDA Outstanding Contribution Award.  He received his degrees from the Univ. of Buffalo (1979); Massachusetts Institute of Technology (MIT); and from Univ. of Vermont. He supported semiconductor development for IBM, Qimonda, and TSMC corporations. He presently founded a limited liability corporation (LLC) consulting business supporting ESD design, teaching, and patent litigation.  He is an ESDA Board of Directors, Education Committee member, and WG5.5 TLP Chairman; author of the books. Physics and Devices,  ESD: Circuits and Devices, ESD: Radio Frequency (RF) Technology and Circuits,  Latchup, Silicon Germanium: Technology, Modeling and Design,  recipient of 175 US patents. He initiated the ESD on Campus  program visiting 31 universities (US, Singapore, Taiwan, Malaysia, Philippines, Thailand, and China).