What are the limitations of EDA tools?

In Part 1 of the article, we reviewed what EDA tools are good for. Here we will discuss EDA tool limitations.

A complete ESD solution is never made by EDA tools alone. Certain ESD design aspects are so specific for a product that it does not pay to make an EDA code for it (although it could fundamentally be done).

ESD is a complex phenomenon and ESD design verification involves checking a wide range of initial conditions and requirements (e.g., available area, stress tests validations conditions, single or cumulative stresses, special bonding or package conditions, external metallization levels, etc.). These require special inputs and appropriate initializations in EDA tools which often prevents ESD EDA from being a push-button solution. ESD protection strategies vary, and an EDA tool cannot always establish a priori the best strategy out of several existing ones.

Many ESD events are characterized but not properly modeled. An example is a parasitic thyristor or bipolar which is triggered during ESD stress (Figure 1). There is no “full” model available which can be integrated into an EDA tool. The trigger and holding properties of the device (V_t1 and V_H in Figure 2) depend on the geometry, the substrate currents, and many other parameters. The ESD designer, however, can still manage the design by interpolation of test structure data, or rely on experience from previous products. This “data gap” sets a fundamental limitation to the use of EDA tools for complete ESD design.

Figure 1: Cross-section of a parasitic thyristor between a PMOS at VDD and a grounded n-well cap. This phenomenon is well-known, but prediction of the exact trigger point and holding voltage is hard due to the many parameters involved.

Figure 2: Trigger and holding characteristic in a generic ESD design window [3].

It is important to use the most suitable type of EDA tool for a given verification task.

Static ESD checks are based on predefined, hard-coded ESD rules. The rules are usually defined with worst-case assumptions that can lead to over-engineering and unnecessary design margins.  Moreover, the ESD rules encoded in static check tools are usually suitable for typical driver architectures or power-supply protection. Custom ESD codesign (e.g., for specialized high frequency, mixed voltage, fail-safe, or low leakage designs) may not be supported by standardized static checks. For those non-standard interfaces, the ESD codesign relies on electrical simulations of circuit performance with the ESD network for better matching. The utilization of static checks may not guarantee the required circuit performance.

Dynamic ESD checking tools are more suitable for the ESD codesign. These tools perform ESD circuit simulations using regular schematics or schematics with extracted s-parameter or resistive networks. These simulations require the expertise of a design engineer and ESD specialist to correctly set them up and analyze the results.

Still, dynamic EDA tools run into multiple limitations, especially when simulating ESD events for full chips rather than special IPs. These limitations are especially obvious when meeting complex ESD requirements, such as Charge Device Model (CDM) ESD in low-cap high-frequency design [1].

Current paths in bulk and metallization are not always accurately assessed. For example, the fast CDM current transients in the range of even 20-300ps in power and ground line cause voltage overshoots on inductance of metal lines. Contemporary dynamic ESD simulators are not capable of performing inductivity extraction for the power and ground mesh on a full chip or even a large power mesh. Thus, dynamic CDM simulations might be inaccurate or executed only on a part of the IP.

While the energy of CDM discharge usually stays the same for different pins, the waveform shape can vary significantly for different pins. Package trace can change its duration between 0.5-2ns [2]: for longer CDM pulses, current magnitude will be reduced to maintain the same energy. Different circuit components may be sensitive to either higher voltage drop originating due to higher current, or higher thermal dissipation during longer CDM discharge pulse. Setting appropriate voltage/current limits in the simulation/verification poses additional EDA challenges.

In conclusion, defensible design decision-making is data-driven. We may not always have all the data that we want, but understanding design margins and areas of risk (particularly during IP design and full-chip assembly) is key to providing guidance for the creation of robust and reliable IC designs. ESD engineers often provide that guidance to circuit and layout designers. Over the last decade, EDA tools and the coverage that sign-off EDA rule decks provide have come a long way in creating a robust baseline for reliability (especially in the field of ESD) for full-chip designs where simulation and less robust techniques (visual inspection) are not practical or advisable [3]. Some of these rule decks are provided by foundries. For those companies that do not prescribe to foundry-provided methodologies, many have invested in automating checks themselves, based on their own custom criteria. There will always be corner cases and requests to waive a specific rule as part of larger design considerations. EDA tools significantly improve productivity and confidence within the design community, but there will always be a need for specialist oversight and evaluation of results against reasonableness and provide professional judgment for waivers. This is particularly true for results that are close to or failing agreed-upon design margins. EDA Tools alone? No! But coupled with capable engineers, EDA tools provide an incredible productivity gain and insight into at-risk areas of IC designs.

References

1. U. Ishfaq, K. Domanski, S. Heber, and H. Gossner, “Advanced CDM Simulation Methodology for High-Speed Interface Design,” 2022 44th Annual EOS/ESD Symposium
   (EOS/ESD), Reno, NV, USA, 2022, pp. 1-6, doi: 10.23919/EOS/ESD54763.2022.9928517.
2. D. Johnsson, K. Domanski, and H. Gossner, “Device Failure from the Initial Current Step of a CDM Discharge,” 2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Reno, NV, 2018, pp. 1-7.doi: 10.23919/EOS/ESD.2018.8509779.
3. M. Khazhinsky, et al, “Technical Report for ESD Electronic Design Automation,” ESDA Technical Report ESD TR18.0-01-14, 2014.
   

	Michael G. Khazhinsky is currently a Principal ESD engineer/designer at Silicon Labs in Austin, Texas.
	Eleonora Gevinti is a Senior Engineer in developing ESD EDA checks addressed to Smart Power BCD ICs at STMicroelectronics.
	Krzysztof Domanski a Principal Engineer in the field of ESD/Latchup on chip and system level at Intel.
	Guido Quax is part of the ESD team of NXP Semiconductors, focusing on high voltage ESD solutions, EDA tools, and (transient) latchup.
	Matthew Hogan is a Product Management Director for Calibre Design Solutions at Siemens Digital Industries Software.
	Founded in 1982, EOS/ESD Association, Inc. is a not for profit, professional organization, dedicated to education and furthering the technology Electrostatic Discharge (ESD) control and prevention. EOS/ESD Association, Inc. sponsors educational programs, develops ESD control and measurement standards, holds international technical symposiums, workshops, tutorials, and fosters the exchange of technical information among its members and others.