Characterization for ESD Design, the TLP Zoo: Part 1
Author’s Note: This is the first of a two-part series on the TLP Zoo, the variety of transmission line pulse (TLP) systems used in the characterization of electrical components and system of ESD robustness. In this article, the motivation for TLP measurements will be discussed, followed by TLP basics and the most widely used TLP configuration, time domain reflection (TDR). The second article will cover several alternative TLP configurations, including Kelvin, time domain reflection and transmission and current source TLP, and the importance of a TLP system’s load line. The second article will also introduce two extensions of TLP testing that have been proposed for testing integrated circuits for charged device model (CDMJ) robustness as well as present some additional TLP resources.
Introduction
Electrostatic discharge (ESD) events are high current events that occur over a short period of time. Components such as integrated circuits and electronic systems need to be designed and then tested to ensure that they can survive the ESD events they may experience during their lifetime. Integrated circuits are tested using the human body model (HBM) [1] and charged device model (CDM) [2], while systems are tested using IEC 61000-4-2[3]. A comparison of the waveform characteristics of the three stresses is shown in Figure 1 where stress levels have been adjusted to make the waveform comparisons easier to visualize. HBM involves stress currents on the order of 1 amp with a characteristic length of 150 ns. The waveform in Figure 1 is shown for a 2 kV stress. Today’s products are considered ESD robust for handling in an ESD protected area if it passes a 1 kV stress. CDM produces several amps of current lasting on the order of 1 ns. The 4 A stress shown in Figure 1 is a typical stress level for a moderate sized package. The system level stress illustrated in Figure 1 is for a 1 kV stress. Typical stress levels for system level testing are often at 8 kV.
Figure 1: Comparison of ESD test waveforms
Designing to protect against these levels of stress requires knowledge of device properties at high currents but short times. Producing and measuring such pulse currents and voltages presents a unique challenge. The challenge was answered by Tim Maloney and co-authors in two landmark papers published in 1985 [4][5], the transmission line pulse, TLP, measurement system. With TLP current versus voltage and current and voltage time dependence can be measured in the ESD range of currents and time duration for all three of these ESD stress waveforms. TLP, however, is not just one system, there are a variety of TLP configurations, each with its own advantages and disadvantages. This series will introduce TLP measurement and explore some of the TLP variations in the TLP Zoo.
In the subsequent discussion all coaxial cables are assumed to be 50-ohm cables. It is also important to note that since TLP measurements have both high voltages and currents, it is important to incorporate appropriate attenuators at oscilloscope inputs to prevent damage. For simplicity, these attenuators are not shown. In all figures, current sensors are depicted by an oval around the center conductor and voltage probes are depicted by an arrow with a sense resistor. Connections to the oscilloscope are assumed to be 50-ohm coaxial cables.
The (Over) Simplified TLP System
Figure 2 shows a schematic of a simplified TLP system. TLP works on the principle that a coaxial cable charged to a voltage will produce a square pulse with a current into a short equal to the charging voltage divided by the impedance of the coaxial cable with a duration equal to twice the propagation length of the cable. A 10 m long 50-ohm cable charged to 100 V will produce an approximately 100 ns, 2-amp pulse. Measuring the voltage across the device and the current through the device with appropriate voltage and current probes and a high-speed oscilloscope allows one to determine the current versus voltage characteristics of the device under test (DUT).
Figure 2: (Over) simplified TLP system for a 100 ns pulse
Figure 3 illustrates the most common data that is obtained from a TLP measurement, a pulsed I-V curve. Pulses are made with increasing charging voltage and the voltage and current are averaged over a period late in the pulse. Each pulse creates a current versus voltage data point. Plotting the pulses maps out the IV curve. Figure 3 is for a device with snapback characteristics such as a grounded gate nMOS device. For stress voltages below avalanche, breakdown currents are low. Current increases when avalanche breakdown begins. Eventually, avalanche breakdown triggers the nMOS device’s parasitic npn device into a non-destructive snapback state. At high enough currents, the device can be damaged, which may be reflected in a second drop in voltage. Most TLP systems include the capability to measure device leakage after each pulse to detect device damage. In this manner, the TLP simultaneously serves as a valuable tool to understand the device physics and the parameters that dictate the snapback behavior.
Figure 3: Sample IV curve from a TLP measurement
The system in Figure 2 neglects the effects of multiple reflections which can occur in a TLP system. Unless the DUT has the same impedance as the cable delivering the pulse, usually 50 ohms, there will be reflections that can last for several times the pulse duration. These reflections can damage the DUT at currents well below the DUT’s maximum capability, masking the DUT’s true capability. For this reason, TLP systems require some method to remove reflections. Several methods have been developed to remove reflections and some of them will be discussed in these two articles.
Other factors result in a proliferation of TLP types. TLP systems are high speed systems requiring signal paths that maintain a constant impedance except for the DUT itself. The challenges of high-speed measurements are especially true for pulse lengths below 10 ns, to the extent that such systems get their own name, very fast TLP (vf-TLP). The characteristic impedance of the TLP system can also affect the resultant measurement, potentially hiding important characteristics of the DUT. To explore the challenges and solutions in TLP measurements, several TLP variations will be discussed, time domain reflection in this article and several other configurations in Part 2.
Time Domain Reflection TLP
The most common form of TLP is the Time Domain Reflection (TDR) system shown in Figure 4. This is essentially the same as that shown in Figure 2 except for the insertion of the attenuator, which is frequently about 6 dB, reducing the signal by half. This is a good time to describe what happens during a single TLP pulse.
Figure 4: Time Domain Reflection (TDR) TLP system for standard or vf-TLP
The transmission line is first charged to a voltage. The relay S is then closed, initiating the pulse. The pulse travels through the attenuator and is measured by the oscilloscope using current and voltage probes. The pulse continues to the DUT where some of the current passes through the DUT and the remainder of the pulse is reflected back towards the pulse source. The reflected pulse is then measured again by the voltage and current probes. The pulse then travels back through the attenuator, travels the full length of the transmission line, is reflected back toward the DUT passing through the attenuator for a third time. The second and third passes of the pulse through the attenuator ensure that after the initial stress on the DUT each subsequent stress is reduced by at least a factor of four.
In TLP systems the voltage and current probes are often placed some distance from the DUT. This is done because it is often easier to maintain a constant impedance at the position of the probes at a position away from the DUT. This is especially true when doing wafer probing. To determine the voltage and current at the DUT, it is necessary to rely on the reflection properties of signals traveling in coaxial cables when they meet a change in impedance. These properties are described by the following equations, where VI and II are the incident voltage and current, VR and IR are the reflected voltage and current, and ZCable and ZDUT are the cable and DUT impedances.
The voltage and current which the DUT experiences is the sum of the incident and reflected signals. The TDR method can be used for standard, 100 ns pulse length, TLP, and for vf-TLP with pulse lengths in the 5 ns or shorter range. How the signals are handled is different for 100 ns TDR and for 5 ns TDR, as shown in Figure 5.
Figure 5: TDR oscilloscope traces for standard and vf-TLP for a DUT with impedance less than 50 ohms
For a 100 ns TLP pulse the pulse length is long enough that the incident and reflected pulses overlap at the position of the probes. Since the incident and reflected pulses overlap at the probe positions, the voltage and current can be directly measured during the overlap period. Typically, the voltage and current are averaged over a time window late in the overlap period. This method creates high quality I-V curves of the type discussed in Figure 3.
This cannot be done with vf-TLP because the pulse length is too short for there to be sufficient, or any, overlap at the probes of the incident and reflected signals. For vf-TLP it is necessary to have the probes and DUT sufficiently separated that the pulses have no overlap. The digital data from the oscilloscope is used to time shift the incident and reflected pulses numerically and then add them together to obtain the voltage and current experienced by the DUT. An advantage of the vf-TLP method is that the time dependence of the voltage and current can be observed directly in the added signals. The disadvantage is that vf-TLP I-V curves are often much noisier than for 100 ns TLP. This is because for a low resistance DUT the vf-TLP voltage measurement is the subtraction of two large numbers while the 100 ns TLP is a direct measurement. In vf-TLP care must also be taken to obtain the proper amount of time shift when adding the incident and reflected signals or critical time dependent features can be distorted.
The above discussion for TDR TLP implies that the 100 ns TLP and vf-TLP measurement systems are the same except for the length of the charged cable which determines pulse length. This is true in principle but usually not in practice. Measuring I-V curves with 100 ns TLP is relatively forgiving of less-than-ideal test fixturing. Short clip leads and standard wafer probes can be used to connect from the coax pulse source to the DUT. The voltage probe can be a standard 500 MHz oscilloscope probe and the current probe can be a Tektronix CT1 probe in an appropriate fixture. This is not the case for vf-TLP, where maintaining 50-ohm impedance right up to the DUT is critical. For wafer level measurements, RF probes become a requirement. To obtain the required bandwidth for voltage measurements, voltage pickoff Tees with resistances between 1000 and 5000 ohms are used rather than oscilloscope voltage probes. For vf-TLP current measurements are often obtained from the voltage data using I = V/50 ohms due to bandwidth limitations of current probes. In 100 ns TLP with overlapping incident and reflected pulse, device current cannot be determined from the voltage measurement because the voltage does not contain the needed directional information for a current measurement. In vf-TLP with separated incident and reflected currents, the directional information is known.
Summary
In this article, some of the fundamental aspects of TLP testing have been introduced along with the most widely used TLP configuration, time domain reflection. The second article, to be published next month, will introduce more members of the TLP Zoo, Kelvin TLP, time domain reflection and transmission TLP, and current source TLP. The importance of a TLP system’s characteristic impedance will also be covered. Finally, two extensions of the TLP Zoo that promise improved CDM testing at low voltages where the traditional field induced CDM test methods have limitations will be discussed. A section on additional TLP reference documents will be included.
References
- “For Electrostatic Discharge Sensitivity Testing Human Body Model (HBM) – Component Level,” ANSI/ESDA/JEDEC JS-001.
- “For Electrostatic Discharge Sensitivity Testing Charged Device Model (CDM) – Component Level,” ANSI/ESDA/JEDEC JS-002.
- “Electromagnetic compatibility (EMC) – Part 4-2: Testing and measurement techniques – Electrostatic discharge immunity test,” IEC 61000-4-2.
- N. Khurana, T. Maloney, and W. Yeh, “ESD on CHMOS Devices – Equivalent Circuits, Physical Models and Failure Mechanisms,” Proceedings of 23rd International Reliability Physics Symposium, 1985.
- T. Maloney and N. Khurana, “Transmission Line Pulse Techniques for Circuit Modeling of ESD Phenomena,” Proceedings of the EOS/ESD Symposium, 1985.
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