Commercial Versus Automotive ESD Integrated Circuit Qualification: Part 2

Introduction

This is Part 2 of an article describing the difference between the electrostatic discharge (ESD) qualification requirements for automotive and standard commercial integrated circuits. Part 1 of the article, in last month’s issue of In Compliance, described why it is reasonable for automotive products to have higher qualification requirements, describes the documents that specify the requirements for commercial and automotive integrated circuit qualification and the high-level differences between ESD qualification for automotive and commercial integrated circuits. Part 2 describes the additional requirements for automotive ESD testing for human body model (HBM) and charged device model (CDM).

(This article had its origin in a series of blog posts on ESD testing.)

Note: This article will summarize the differences between automotive and commercial ESD testing of integrated circuits but should not be used as a substitute for a thorough reading of the actual test methods.

HBM

HBM testing is specified by ANSI/JEDEC/ESD JS-001 [1] with additional requirements specified in AEC–Q100-002 REV-E [2]. This section summarizes the additional requirements for automotive HBM testing.

Waveform Requirements (Q100-002 Section 1.1)

The tester must meet the waveform requirements at all test levels. (Legacy wording in JS-001 could be interpreted that the tester didn’t need to meet all waveform requirement at all voltages, but this was never the intention.)

Test Fixture Board Qualification (Q100-002 Section 2)

Requires the test fixture board to meet waveform requirements at all test voltages, not limited voltages. Also specifies requalification if the board is repaired.

Device Stressing (Q100-002 Section 3)

Requires that device stressing be done at 500 V, 1000 V and 2000 V. Levels may not be skipped. JS-001 allows testing at a single level to establish the immunity level. Q100-002 also specifies that if the device fails 500 V, it requires testing at 250 V, and if that fails testing at 125 V if the tester can meet the waveforms.

Devices with 6 pins or less (Q100-002 Section 4.1)

Devices with 6 pins or less must be tested with all pin pair combinations. (One pin on Terminal A and one pin on Terminal B.) JS-001 requires that discrete devices be tested with all pin combinations and allows devices with 10 or less pins to be tested with all pin pair combinations.

Pin Combination Table (Q100-002 Section 4.2)

JS-001 includes two options for pin combinations. Table 2B is the traditional pin combinations from the original version of JS-001 and is the same set of pin combinations as in the now obsolete HBM standards from JEDEC and ESDA. Table 2A is a new table which reduces the number of stresses on an integrated circuit but requires more understanding of the device under test. The purpose of Table 2A is to reduce test time and, possibly more important, to reduce failures due to wear out. Q100-002 requires all testing to start using Table 2B. Q100-002 does give three situations in which Table 2A may be used.

A low parasitic tester is being used

If a failure using Table 2B is deemed to be a false failure

If the use of Table 2B leads to failures from wear out due to cumulative stress

Low Parasitic Tester (Q100-002 Section 4.3)

Q100-002 has special instructions if using a low parasitic tester such as a two-pin tester.

Connectivity must be verified for each stress

Non-supply to non-supply stress may be done using Table 2A

All adjacent non-supply pins must be stressed versus each other

The options in JS-001 Section 6.6 for low parasitic HBM testers may be used.

Reporting (Q100-002 Section 5.0)

Q100-002 has a section on reporting, which is lacking in JS-001. In addition to reporting the basic test results the reporting section requires information on the type of tester used, details on the samples and test details such as pin groupings, stress voltage levels, any partitioning of stress over multiple devices, stress pin combinations, and any exceptions for the tests performed.

CDM

CDM testing is specified by ANSI/JEDEC/ESD JS-002 [3] with additional requirements specified in AEC-Q100-011 Rev-D [4]. This section summarizes the additional requirements for automotive CDM testing.

Stress Levels Tested (Q100-011 Sections 2.3 and 2.5)

250 V is a required test level, and if higher withstand levels are to be reported testing must be done in 250 V increments up to the highest passing level. It is not permissible to skip stress levels. If a device fails at 250 V testing is to be done at 125 V and if failure occurs at that level lower levels such as 100 V and 50 V are to be used. JS-002 allows testing at a single voltage and if all requirements are met that level can be used as the devices CDM withstand level.

Discharge Requirements (Q100-011 Section 2.5)

One of the most significant differences between JS-002 and Q100-011 is the number of zaps to each pin per voltage and polarity. Q100-011 requires 3 stresses on each pin for each voltage and polarity, while JS-002 requires “at least 1 discharge” per voltage and polarity. The wording of “at least 1 discharge” was added to JS-002 so that a single set of testing could cover both JS-002 and AEC Q100-11 testing.

Corner Pin Classification (Q100-11 Sections 1.3.1 and 2.6)

A unique feature of the AEC CDM is the corner pin requirement. As discussed in Section 2 the standard qualification level for CDM is 500 V, with corner pins at 750 V. Section 1.3.1 of AEC Q100-11 describes the definition of a corner pin, while Section 2.6 describes two methods to determine the 750 V corner pin classification.

Small Package Considerations (Q100-11 Section 2.7)

This section of Q100-11 discusses the difficulties of CDM testing of small package, and notes that in some cases the testing may need to be skipped, but this must be noted and done in agreement with the user. AEC-Q100-011 Rev-D was published before JS-002-2018 added provisions to eliminate further CDM testing of small devices within a technology family with a known CDM history of robustness.

Wafer or Bare Die Considerations (Q100-11 Section 2.8)

This section discusses CDM testing of products shipped at wafer level or as bare die. The document allows bare die product to be tested in a surrogate package if the package used is documented.

Failure Criteria (Q100-11 Section 2.9)

This section defines failure as not meeting all device specifications. The section also notes that after CDM testing device parameters can drift from out of specification back into specification. This section encourages post stress testing to be done soon after stress but does not give a time limit.

Acceptance Criteria (Q100-11 Section 2.10)

This section requires that devices classified at a particular level not only has to pass that level of stress but also must pass all lower stress levels.

There are also some slight differences in the classification levels between JS-002 and Q100-11. To account for the 750 V corner pin requirement, AEC has inserted an extra level into their classification scheme, creating some confusion. The new Q100‑11 level of C2 has the same definition as the JS-002 definition as JS-002 level C2a. To obtain the C2a level in Q100-11 requires corner pins passing 750 V or higher.

Table 1: Comparisons of JS-002 and Q100-11 qualification levels

Summary

In summary, the ESD requirements for commercial versus automotive qualification are very similar. Both require HBM and CDM testing based on the same two test standards, JS-001 for HBM and JS-002 for CDM. Automotive qualification has additional requirements, including specified qualification target levels, 3 versus 1 zap for CDM, and several additional requirements. The good news is that if a product has met the requirements of AEC Q100 for ESD qualification, the product will more than met the requirements for JEDEC/ESDA qualification for ESD.

References

1. ANSI/ESDA/JEDEC JS-001-2017, “For Electrostatic Discharge Sensitivity Testing, Human Body Model (HBM) – Component Level,” EOS/ESD Association and JEDEC Solid State Technology Association.
2. AEC–Q100-002 REV-E, “Human Body Model Electrostatic Discharge Test,” Automotive Electronics Council.
3. ANSI/ESDA/JEDEC JS-002-2018, “For Electrostatic Discharge Sensitivity Testing, Charged Device Model (CDM) – Device Level,” EOS/ESD Association and JEDEC Solid State Technology Association.
4. AEC-Q100-011 Rev-D, “Charged Device Model (CDM) Electrostatic Discharge (ESD) Test,” Automotive Electronics Council.

About The Author

Robert Ashton

Robert Ashton is the Chief Scientist at Minotaur Labs. He received his BS and PhD degrees in Physics from the University of Rhode Island. After Post-Doctoral positions at Rutgers University and Ohio State University he joined AT&T Bell Laboratories in the field of integrated circuit technology development. He stayed with Bell Laboratories, and its spinoffs Lucent Technologies and Agere Systems for 23 year where he became involved with on chip ESD protection. After leaving Agere Systems he became Director of Technology of White Mountain Labs, an ESD and latch-up test house. He then spent 10 years with ON Semiconductor in their discrete products division, providing and managing application engineering support for transient voltage suppression products. He has published numerous articles on ESD testing of integrated circuits, test structure use in integrated circuits, and CMOS technology development. He has also presented tutorials on ESD, latch-up, and transmission line pulse testing at IEEE and ESDA conferences. Robert is an active member of ESDA working groups for device testing standards and the JEDEC latch-up working group. He has been a regular member of the EOS/ESD Symposium technical program committee. Robert served on the ESDA board of directors from 2011 to 2013 and was business unit manager for advanced topics in 2012 and 2013. He is currently serving as co-chair of the human metal model (HMM) working group.