Component Modeling for System-level ESD Simulation

Q: Why does the Industry Council on ESD Target Levels advocate using SPICE-like circuit simulation to evaluate system-level ESD reliability [1]?

A: This is a time-saving alternative to first identifying problems at the time of ESD qualification testing and remedying those by an inefficient trial and error process. Using circuit simulation for virtual prototyping of system ESD reliability is referred to as system-efficient ESD design, or SEED [1].

Q: What are the roadblocks to system-level ESD simulation?

A: Suppliers of microelectronic components generally do not provide ESD models of their components.

Q: Have any workarounds been proposed?

A: It has been suggested that empirical models can be fit to TLP (transmission line pulse) I-V measurement data [1]. 

Q: How are those empirical models classified?

A: Most are piecewise linear models. More advanced non-linear models have also been investigated, such as recurrent neural networks.

To simulate system-level ESD, all of the microelectronic components along the discharge path must be modeled; these may include a transient voltage suppressor [2], ferrite choke [3], or other discrete components. This article focuses on integrated circuit components. If the ESD-induced voltage and current waveforms at the IC pins are simulated with reasonable accuracy, one can check whether the part will be driven outside its safe operating area or will suffer thermal failure [4][5]. Such an analysis is sufficient to determine whether the IC will avoid hard failure during ESD qualification testing.

Component response to ESD is often assessed using transmission line pulse (TLP) testing [6]. The pulse I-V curve should be measured in both the power-off and power-on states, which necessitates that the device under test, i.e. the IC, be mounted on a test board with a power supply. Ref. [7] contains an example test board design. Typically, the pulse I-V curve is fit to a piecewise linear model [8]. The resulting model is a static model because an I-V curve does not provide information about the dynamic response of the device under test.

If the IC’s transient response is linear then, in principle, the static model can be augmented with a transient model obtained from S-parameter measurements. In many cases, the transient ESD response of an IC is dominated by the parasitic inductive and capacitive elements of the package. In such cases, it may not be necessary to do any measurements to obtain the transient model, because the IBIS model provided by many IC suppliers includes a description of the package. The piecewise linear model obtained from TLP measurements and the RLC package model can be connected together to form a complete ESD model of the component [7], as illustrated in Figure 1.

Figure 1: Conceptual drawing of an ESD model that is constructed using TLP I-V data and package information from the IBIS model. Figure reprinted from [7].

A component model that is comprised of a static I-V model plus a package model well predicts the IC’s transient response to the square-shaped current pulse produced by a TLP tester in many cases, but not all [7]. That finding suggests that the dynamic, nonlinear response of the on-chip semiconductor devices is not always obscured by the dynamic response of the package impedances.

It is very challenging to create an accurate model of a chip’s dynamic response to ESD on the basis of measurement data, i.e., the measured transient response of the packaged IC to ESD-type current pulses, in part because one cannot place probes precisely at the IC inputs when the IC is mounted on a circuit board. The IC designer can more easily create the component ESD model. The designer’s model would consist of the chip netlist, along with compact models of the devices; see, for example, [9]. However, IC suppliers are reluctant to provide such models to their customers because those could disclose intellectual property (IP). It is worthwhile to consider whether the accurate transient model can be reformulated as an IP-obscuring behavioral model. One such candidate model is the recurrent neural network.

A recurrent neural network (“RNN”) is a universal approximator for nonlinear state space systems; such systems are described by ordinary differential equations. An RNN is especially well suited for processing time series data, such as those provided by laboratory instruments or circuit simulators. The RNN model of an IC IO pin is formulated as

The input, u, may be either current or voltage, and the output y is the other quantity, i.e. voltage or current. W_r, W_u, W_y , b_u and b_y are the model parameters. x denotes the internal states of the system. For example, if the system being modeled is a single diode, the variable mapping might be voltage as u, stored charge as x, and current as y. In actuality, the user does not specify a mapping from a physical quantity to the RNN model’s internal state; instead, the internal state is “learned” from data and need not correspond to an identifiable physical quantity. Figure 2 provides a pictorial view of an RNN.

Figure 2: Block diagram illustrating a recurrent neural network (RNN). k is the number of inputs. Linear combinations of the inputs are passed through a nonlinear activation function, such as a sigmoid or tanh. The resultant n-dimensional vector is referred to as the internal, or hidden, state of the system. It is fed back to the input. The output is a linear combination of the hidden state components. When modeling an IO pin, the number of inputs (k) and outputs (m) are both 1; the model input is the ESD current injected into the pin and the model output is the induced voltage (or vice versa).

RNN models can be implemented in Verilog-A [10] and then simulated using commercial circuit simulators, such as ADS, HSPICE and Spectre.

To illustrate the feasibility of transient behavioral modeling, training data were generated by simulating the netlist for a full-chip ESD protection network. Using those data, an RNN model of the circuit was derived using open-source optimization software. Figure 3 shows simulation results obtained using both the netlist description of the circuit and the RNN model. The error associated with the behavioral model is small, less than 3%. One should note that the stimulus applied to the circuit in the simulation of Figure 3 was not included in the training data. It is important to demonstrate that a behavioral model is generalizable, i.e., that it predicts the correct behavior in response to previously unseen stimuli.

Figure 3: Full chip ESD protection network. An RNN model is derived for this circuit and then implemented in Verilog-A. More specifically, a gated recurrent unit (GRU) type RNN structure is used [14]; a GRU is less likely to suffer from the vanishing gradient problem during training than is a basic RNN. The response of the RNN (GRU) model to a randomly-varying piecewise linear voltage source is simulated and compared with the simulation results obtained using the complete circuit netlist.

Although the benefits of a transient behavioral model are clear, more work is needed to determine whether an RNN is the most suitable model for representing a component’s ESD response. Although the RNN is considered a “universal” model, it presents some difficulties, e.g., one must ensure that the learned network is stable for all input stimuli.

TLP provides a one-port I-V measurement, and therefore a model that is extracted from TLP I-V measurement data is a one-port model. It is important to note that the pulse I-V curve measured at an IC pin does not only describe the IC; instead, it describes the combined effect of the IC and the board-level current path(s). Current that flows into an IO pin of an IC divides among the possible return paths in a proportion that is affected by the impedance of the board-level power delivery network (PDN) [11]. Therefore, as shown in Figure 4, the I-V characteristic measured at an IC pin is affected by the board PDN impedance. If multi-port ESD models of components are substituted for the one-port models used today, the full effect of a system’s circuit board can be captured in simulation. Even if the PDN impedance is so low that the board has negligible effect on the measured I-V, a multi-port model of the IC may be needed for soft failure analysis.

Figure 4: TLP I-V was measured at an IO pin of a commercial IC. The IC was mounted on a test board that has a large decoupling capacitor mounted near the voltage regulator and additional SMD capacitors placed near the IC supply pins; the total value of the “additional” decap is indicated in the figure legend. The measured I-V characteristic is observed to change as the amount of supply decoupling capacitance near the IC pins is varied.

During qualification testing, about half of system-level ESD failures are soft failures [1]. Many of those failures are due to noise (“glitches”) that appears at IO pins, a result of magnetic coupling between bond-wires or package traces [12]. A time-domain electromagnetic simulator can perform noise coupling analysis. Assume that the ESD current enters the IC primarily at a signal pin; the on-chip protection network will shunt the ESD current back to the package (and then the board). Therefore, it is the on-chip circuits that determine which combination of package bond-wires or traces constitute the return paths, and noise coupling simulation at the package level should comprehend the effects of the chip. EM simulators do not provide such capability, but a hybrid EM-circuit simulator can be used. In [13], the Speed2000 simulator was used to simulate ESD-induced noise coupling to signal lines inside an IC package; sample results are shown in Figure 5.

Figure 5: In simulation, the IO0 signal pin of an IC is subjected to an IEC 61000-4-2 contact discharge. The ESD-induced noise at three “non-zapped” signal inputs is plotted; the noise is measured at the die-level bond pad. The noise is generated by magnetic coupling inside the package. Figure reprinted from [13].

Over the past 5 or 6 years, industry and university researchers have advanced the state of the art in system-level ESD simulation, and this article provided an overview of some of those activities. Much work remains to be done to establish repeatable and accurate methods to characterize component response to system-level ESD, and to achieve consensus as to the most suitable model structure.

The authors acknowledge the support of the Center for Advanced Electronics through Machine Learning (CAEML) and the National Science Foundation (under CNS 16-24811).

References

1. JEDEC, “System Level ESD Part I: Common Misconception and Recommended Basic Approaches,” JEP-161.
2. P. Wei, G. Maghlakelidze, A. Patnaik, H. Gossner and D. Pommerenke, “TVS transient behavior characterization and SPICE-based behavior model, in EOS/ESD Symp. Proc., 2018.
3. D. Johnsson and H. Gossner, “Study of system ESD codesign of a realistic mobile board,” in EOS/ESD Symp. Proc., 2011.
4. T. Li, V. Pilla, Z. Li, J. Maeshima, H. Shumiya, K. Araki and D. Pommerenke “System-level modeling for transient electrostatic discharge simulation,” IEEE Trans. on Electromagnetic Compatibility, vol. 57, no. 6, pp. 1298 – 1308, 2015.
5. C. Russ, M. Ammer and K. Esmark, “Predicting system level ESD robustness using a comprehensive modelling approach,” in EOS/ESD Symp. Proc., 2018.
6. T. Maloney and N. Khurana, “Transmission line pulsing techniques for circuit modeling of ESD phenomena,” in EOS/ESD Symp. Proc., pp. 49-54, 1985.
7. F. Escudié, F. Caignet, N. Nohlier and M. Bafleur, “From quasi-static to transient system level ESD simulation: Extraction of turn-on elements,” in EOS/ESD Symp. Proc., 2016.
8. N. Monnereau, F. Caignet, N. Nolhier, M. Bafleur and D. Tremouilles, “Investigation of modeling system ESD failure and probability using IBIS ESD model,” IEEE Trans. Dev. Materials Rel., vol. 12, no. 4, pp. 599-606, 2012.
9. Y. Zhou, J. Hajjar, S. Parthasarathy, D. Clarke and B. Moane, “System level ESD simulation in SPICE: a holistic approach,” in EOS/ESD Symp. Proc., 2018.
10. Z. Chen, M. Raginsky and E. Rosenbaum, “Verilog-A compatible recurrent neural network model for transient circuit simulation,” in IEEE Conf. on Electrical Performance of Electronic Packaging and Systems, 2017.
11. C. Reiman, N. Thomson, Y. Xiu, R. Mertens and E. Rosenbaum, “Practical methodology for the extraction of SEED models,” in EOS/ESD Symp Proc., 2015.
12. N. Thomson, Y. Xiu, and E. Rosenbaum, “Soft-failures induced by system-level ESD,” IEEE Transactions on Device and Materials Reliability, vol. 17, no. 1,
    pp. 90 – 98, 2017.
13. J. Xiong, Z. Chen, Y. Xiu, Z. Mu, M. Raginsky and E. Rosenbaum, “Enhanced IC modeling methodology for system-level ESD simulation,” in EOS/ESD Symp. Proc., 2018.
14. K. Cho, B. van Merrienboer, C. Gulcehre, D. Bahdanau, F. Bougares, H. Schwenk and Y. Bengio, “Learning phrase representations using RNN encoder-decoder for statistical machine translation,” in Conference on Empirical Methods in Natural Language Processing (EMNLP 2014), June 2014.

Founded in 1982, EOS/ESD Association, Inc. is a not for profit, professional organization, dedicated to education and furthering the technology Electrostatic Discharge (ESD) control and prevention. EOS/ESD Association, Inc. sponsors educational programs, develops ESD control and measurement standards, holds  international technical symposiums, workshops, tutorials, and foster the exchange of technical information among its members and others.

Elyse Rosenbaum is the Melvin and Anne Louise Hassebrock Professor in Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. She received the Ph.D. degree in electrical engineering from University of California, Berkeley. She is the director of the NSF-supported Center for Advanced Electronics through Machine Learning (CAEML), a joint project of the University of Illinois, Georgia Tech and North Carolina State University. Her current research interests include component and system-level ESD reliability, ESD-robust high-speed I/O circuit design, compact modeling, mitigation strategies for ESD-induced soft failures, and machine-learning aided behavioral modeling of microelectronic components and systems.

Dr. Rosenbaum has authored or co-authored nearly 200 technical papers; she has been an editor for IEEE Transactions on Device and Materials Reliability and IEEE Transactions on Electron Devices. She was the recipient of a Best Student Paper Award from the IEDM, Outstanding and Best Paper Awards from the EOS/ESD Symposium, a Technical Excellence Award from the SRC, an NSF CAREER award, an IBM Faculty Award, and the ESD Association’s Industry Pioneer Recognition Award. She is a Fellow of the IEEE.

Zaichen Chen received the B.S. and M.S. degrees in electrical engineering from the University of Illinois at Urbana-Champaign in 2012 and 2016 respectively, where he is currently pursuing the Ph.D. degree. His current research is machine learning based compact model generation for electrical circuits.

Jie Xiong received the B.S. degree in applied physics from the University of Science and Technology of China in 2016. She is currently pursuing the Ph.D. degree in the Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign. Her research interests include compact modeling and system-level ESD analysis.

Published in In Compliance: Hot Topics in ESDhttps://incompliancemag.com/article/component-modeling-for-system-level-esd-simulation/