An Introduction to RF On-Chip ESD Design

As electronic devices of all types continue to shrink in size, electrostatic discharge (ESD) robustness becomes more difficult to achieve. Further, new mobile standards such as 5G are increasing the frequency of operation, with some functions operating at millimeter wave frequencies. These changes pose significant challenges for the ESD protection of radio frequency (RF) components, especially since such protection can interfere with the RF performance of the circuit and rise time clamps cannot be used. Therefore, the protection of RF circuits becomes a delicate balance between robustness and circuit performance.

This article offers an overview of ESD protection design approaches in an RF environment. Those design approaches cover FET vs BJT-based technologies in both GaAs, GaN, and SiGe. Parasitic capacitance, high turn-on voltages, peak-to-average envelop fluctuation of signals and band of operation are all hurdles to RF on-chip ESD design. These metrics will change depending on the location of the protection clamp since the RF signal changes in amplitude and composition at different locations on the circuit. The associated hurdles involved in co-design, a potential alternative, are also discussed.

Introduction – RF Concepts that Affect the Design Space

The fundamental RF design concept is impedance matching [1]. When proper impedance is not maintained, forward power will be reflected, causing poor performance of the RF circuit. As in DC circuits, maximum power transfer is achieved by having the load resistance match the source resistance. To achieve this at RF frequencies, the impedances at any interface should be the complex conjugate of each other as shown in Figure 1 [2].

Figure 1: Maximum power transfer for complex impedances

Placing an ESD clamp on any node can degrade the impedance match of the design because of clamp parasitics. However, if the ESD clamp is co-designed with the matching network of the RF circuit, the parasitics of the ESD clamp can be used in designing these networks. Unfortunately, co-design is a hurdle for many companies, even those with hundreds of RF designers, since there are typically a limited number of professionals with ESD expertise. The more typical

arrangement is to have the ESD designer implement clamps that have low parasitics and consume the smallest area possible. These clamps are then implemented in the associated process design kits (PDKs) that are released to the design community. It can be impossible to co-design a clamp for every product in a company when there are very few ESD engineers.

The other important characteristic of clamp design is to make sure the clamp is off during normal operation. In typical analog and digital circuits, the signal never exceeds the supply rails. The opposite is true of an RF circuit. Figure 2 illustrates a simple RF circuit. Here the power amplifier transistor’s collector there is an inductor, not a bias resistor. This implementation serves two purposes. Resistors dissipate power, therefore reducing efficiency, and inductors block RF signals. The inductor looks like a very high impedance at the RF frequency; hence, this is called an RF choke since no RF will get to the power supply with the choke in place. In this scenario, the instantaneous voltage at the collector can exceed the power supply since the power supply is isolated from the RF signal [3].

Figure 2: RF bias network with an inductor in the collector for an RF choke

Digitally modulated RF signals also have envelope fluctuation that is characterized by a quantity called peak-to-average power ratio (PAPR). Figure 3 illustrates that quadrature phase shift keying (QPSK) has the most envelop fluctuation in this example, whereas gaussian minimum shift keying (GMSK) has none.

Figure 3: Illustration of envelop fluctuation, relation to the constellation diagram and PAPR for typical modulation formats

The amount of envelop fluctuation can also be seen visually by the constellation diagram [4]. As the envelope fluctuates, neither the RF circuit nor the ESD clamp should distort the envelop. In doing so, bit error rates degrade, and spectral regrowth will increase. The instantaneous peak of the envelop divided by the average power of the signal is PAPR. In log form, this calculation is

The current LTE standard uses orthogonal frequency-division multiplexing (OFDM), which has up to 12dB of peak to average fluctuation over the average power. These are critical metrics to know since they are needed to design the proper turn-on characteristics of an ESD clamp for these applications [5, 6].

RF On-Chip ESD Design Considerations

Trigger Voltage Design

Taking a closer look at the collector node in the amplifier circuit illustrated in Figure 2, there are four factors to consider for ESD clamp design: 1) DC voltage, 2) average RF power, 3) PAPR, and 4) parasitic capacitance. The first three factors are needed to design the proper trigger voltage of an ESD clamp. Figure 4 illustrates how to the DC voltage, average RF power and PAPR is converted to a peak voltage. Note that the impedance Z is a function of the RF circuit and is not always 50 ohms. At the collector of a large power amplifier, this impedance can be very small because of the large periphery of transistors in the output stage.

Figure 4: How to determine the clamp trigger voltage on an RF node

Parasitic Capacitance

One of the workhorses in ESD protection is the diode. It has a definitive turn-on voltage and low resistance in the on-state that will sink current without allowing voltage to grow. However, if there is a large voltage on a node during normal operation, several diodes in series would be required to keep the diode stack off during normal operation.

For example, let’s assume that nine diodes in a certain process are needed at a high-power node. Figure 5a illustrates the equivalent on-state characteristic of the diode stack. The on-state resistance (Ron) of this stack is nine times greater than the single diode and becomes ineffective for clamping large voltages. One remedy is to parallel several stacks together to lower Ron. As a result, the paralleled stacks now have a large capacitance.

Figure 5a and 5b are simulations of the clamping characteristics and parasitic capacitance of the diode stacks. 5b is a simulation of a Human Body Model (HBM) event with the different clamps. 5c is the off-state capacitance. Note that while nine diodes in series have lower capacitance, the clamping is poor, whereas using 10 diodes in series offers better clamping but unacceptable parasitic capacitance. Although diodes are an ESD workhorse, they are reserved for DC nodes in RF circuits. Diodes can be used on input nodes where the peak voltages are much lower and parasitics are not as detrimental to the impedance at these nodes. [7, 8]

Figure 5: Diode stacks: a) Ron increases; b) HBM clamp simulation; c) Parasitic capacitance simulation

Diving deeper into parasitic capacitance illustrates its importance in RF circuits. Figure 6a shows a block diagram of a power amplifier (PA) and its output match. The output match’s sole purpose is to transform the low impedance at the collector of the PA to 50 ohms in order to match to the antenna’s impedance. Clamp placement has detrimental effects to this match; however, some locations are more sensitive to parasitics than others. Two examples are highlighted here. In Example 1, the clamp is placed at the collector node (low impedance), while in Example 2 the clamp is placed at the 50-ohm point after the matching network.

The effect of capacitance on the network is illustrated in the results in Figure 6b, which shows the output impedance of the network which is supposed to be at 50 ohms. The impedance on the left plot is the change at the output when a clamp with 1pF of capacitance is placed at the collector. The overall output impedance at the antenna has not changed much. However, capacitance much more than this will degrade the output match. The plot on the right shows the output impedance shift when a clamp of 1pF is placed at the 50-ohm point of the RF chain. Either the RF designer can retune the output match or the ESD designer needs to develop a clamp with lower off-state capacitance.

Figure 6: Parasitic capacitance placed at the collector of the PA vs the 50-ohm output of the PA

In a situation where co-design is impractical, the ESD designer needs to find lower parasitic clamp options. The second workhorse, if it is available in a process, is a snapback device.

Figure 7a shows a snapback characteristic. It has a high turn-on voltage (Vt). After turn-on, the voltage snaps back to a lower, holding voltage (Vh). This voltage is sustained with low Ron until the clamp itself fails. If a process supports BJTs (say a heterojunction bipolar transistor (HBT) process), then snapback clamps are simple, small and effective and offer lower parasitics than diode stacks. Figure 7b shows a typical base-open clamp for the positive protection. The reverse diodes are for the negative protection.

Figure 7c shows an example compact layout of the clamp. A high voltage on the collector causes the collector base junction to breakdown enough to allow the voltage to rise across the base emitter junction and turn the HBT on, thereby shunting the ESD energy to ground. If the stage of the amplifier is also designed with the same device and is large enough, then the entire stage will snapback and self-protect and the base open clamp is not needed. Intermediate stages can benefit from this clamp’s compact size and high voltage turn-on while not perturbing the impedance match at that node.

Figure 7: a) Snapback characteristic; b) Base open clamp; c) Layout

Figure 8 shows the transmission line pulsing (TLP) [9] results for the base open clamp. Figure 8a shows the clamp turns on at 19V. Once on, the clamp snaps back to 6V and protects the amplifier. The clamp fails at about 1.4A which has an equivalent protection of higher than 2kV HBM. Figure 8b is the response of the diodes in the reverse direction. Since the RF trajectory on the collector node will never swing negative, one diode in the reverse direction is sufficient. Note that once proper protection level is achieved, it is imperative that the clamp S-parameters are measured, and a total off-state capacitance is extracted. This capacitance may be more than the models predict due to additional parasitics of the layout which is important information for the designer.

Figure 8: a) Positive TLP of base open clamp; b) Negative TLP where the reverse diode turns on

An HBT process isn’t the only RF process used for mobile applications. Another type of process called pseudomorphic high electron mobility transistor (PHEMT) can be used as well. For enhancement-mode (E-mode) processes, the snapback clamp is very similar. Figure 9a and 9b shows the equivalent E-mode snapback clamp. Similarly, some PHEMT processes are depletion-mode (D-mode) only. Figure 9c shows the equivalent snapback clamp for D-mode processes [10]. Note that in 9c that the pinch off diodes are there to keep the clamp off during normal operation. If the gate of the D-mode FET is floating, the FET will be on and current can flow. However, the diodes require a voltage at the drain high enough to turn them on. The higher the RF power and PAPR, the more diodes are needed, and this will make the clamp larger. It is not as elegant of a solution as in the E-mode or HBT processes.

Figure 9: FET snapback clamps: a) E-mode; b) E-mode low voltage trigger; c) D-mode

There are other variations on this same theme, but the above clamps when sized correctly are aimed to protect 1kV to 1.5kV HBM. At the moment, this is industry standard since static build up in a typical factory setting is well controlled [11]. For those instances where more than 2kV of protection is needed, other solutions are published but are not covered in this article.

Conclusion

The RF design space considerations pose different challenges for on-chip ESD protection. Standard clamps for analog or digital applications will not work in the RF domain. The RF signal itself can reach instantaneous voltages far above the power supply; thus, clamps with very high trigger voltages are needed.

RF design is centered around impedance matching to ensure that power is not reflected at any interface causing performance degradation. Clamps with large parasitics in the off state will degrade an RF impedance match and cannot be implemented. Snapback devices, if available, tend to have high trigger voltages, thus avoiding clipping the RF modulated signal and have low parasitics to maintain proper impedances. RC time constant circuits cannot be used since the RF signal would turn on the ESD clamp. RF and ESD co-design are the optimal situation but are dependent upon access to experienced ESD engineers to implement successfully.

References

1. D. Pozar, Microwave Engineering, 3^rd Edition, John Wiley and Sons Inc, 2005
2. A. Sedra and K. Smith, Microelectronic Circuits, Oxford University Press, 2014
3. S. Cripps, RF Power Amplifiers for Wireless Communications, Artech House, 1999
4. J. Proakis, Digital Communications, 3^rd Edition, McGraw Hill, 1995
5. T. Rappaport, Wireless Communications, Principles and Practice, Prentice Hall, 1996
6. L. Larson, RF and Microwave Circuit Design for Wireless Communications, Artech House Pub., 1996
7. K. Muhonen, “RF Basics, Theory and Lab Measurements,” Course Notes, 2013.
8. D. Teeter, et. al, “GaAs HBT ESD Diode Layout and its Relationship to Human Body Model Rating,” Bipolar/BiCMOS Circuits and Technology Meeting, 2006.
9. J. Barth, et. al., “TLP Calibration, Correlation, Standards, and New Techniques,” IEEE Transactions on Electronics Manufacturing, vol. 24, no. 2, pp. 99-108, April 2001.
10. Q. Cui, et. al. “A Novel Electrostatic Discharge (ESD) Protection Circuit in D-Mode pHEMT Technology,” IEEE Compound Semiconductor Integrated Circuits Symposium (CSIC), 2012.
11. Industry Council on ESD Target Levels, White Paper 1, “A Case for Lowering Component level HBM/MM ESD Specifications and Requirements,” June 2018.

ABOUT THE AUTHOR

Kathleen Muhonen

Kathleen Muhonen is an ESD engineer at Qorvo in Greensboro, NC. She is involved in ESD on-chip protection for RF and Millimeter wave applications. She is also heavily involved in system level testing and helped standardize IED testing of RF components. Kathleen has served on multiple ESD Association device testing standards committees, and has chaired the TLP and HMM workgroups. She has also presented a number of papers at the EOS/ESD Annual Symposium over the last decade. Kathleen holds a BSEE degree from Michigan Technological University, an MSEE from Syracuse University, and Ph.D.EE from Penn State University.