ESD Protection for Mobile RF Front-end Modules

With the advent of wide-spread wireless electronics, the need for high-performance RF components to be built into highly reliable and robust products continues to expand. One of the more challenging subsystems to protect, particularly from electrostatic discharge (ESD), is the RF antenna and its associated components. ESD protection for this subsystem must be addressed at 2 levels. First, the individual components must have device level protection to allow assembly with high yields. Second, the entire subsystem must have the necessary system level (IEC61000-4-2) protection to protect it throughout its use by the end user. While device and system level protection have historically been designed independently, this strategy is being rethought with the ever increasing need for higher performance wireless products. Design of an overall ESD protection architecture necessitates some level of co-design of the device ESD protection in the individual antenna circuit components and the system ESD protection. Finally, the ESD protection must play well with the RF performance of the antenna itself.

Among the components connected directly to the antenna are the antenna tuners and the RF antenna switches that are part of the front end components of the antenna send and receive circuitry. As a cost-effective high-integration solution, RF switches fabricated in SOI CMOS technologies have been widely applied in the RF front end module for mobile products. The RF switch in SOI usually adopts the series-shunt structure which stacks multiple NMOS transistors with relatively low breakdown voltages in series to form paths for high-power RF signals [1-2]. As shown in Figure 1 (a), the gate and body of stacked NMOS transistors in the switch array are connected to high-value resistors and controlled by the signals from the switch controller digital circuit. The layout of a switch array with 14 stacks in series is shown in Figure 1 (b). The NMOS transistor array at every stack varies in width depending on the power that will be transmitted.

Figure 1: (a) the series-shunt structure of SOI RF switch, and (b) the layout of a switch array with 14 stacks 1-mm NMOS array and biasing resistors.

The design of a successful RF switch product not only needs to achieve RF performance measured by such parameters as insertion loss, low harmonic overtones, and isolation optimization; but also needs to consider the final product reliability performance. One of the advantages of the RF switch with series-shunt structure in the SOI technology is the stacked NMOS transistors with high-value resistors can act as a self-protection structure to provide on-chip ESD protection during HBM or CDM ESD events. The shunt switch to ground is needed for improved isolation in the RF switch architecture. This shunt, if designed correctly, can serve as the shunt path for the energy from an ESD pulse. Since the requisite ESD protection is provided by the shunt element that is an integral part of the switch architecture, its additional use as an ESD shunt device comes at no cost to performance.

While the shunt structure is very effective for ESD protection, the mechanism whereby it turns on and carries the ESD energy is rather complex. Much of the mechanism is dependent upon the time constant resulting from coupling of the gate of the transistor array (G_N) and the large gate resistor (R_gN). When there is a positive ESD transient from drain (D) to source (S) of the switch array, the gate coupling effect due to NMOS parasitic capacitors, C_GD and C_GS, will raise the V_GS of the NMOS transistor at every stack above the threshold voltage V_th. Then, the NMOS transistors stacked in series will turn on in the NMOS normal transistor mode to conduct the ESD current and clamp the ESD voltage. However, this transistor conduction is soon overwhelmed by VDS voltage and at least the NMOS arrays higher in the stack will go into “snapback”. In the snapback mode, the parasitic bipolar turns on and the larger ESD current can be shunted to ground [3]. In a negative ESD pulse, the parasitic diodes inherent in the NMOS transistors play a much bigger role in shunting the current to ground. Thus, the self-protection switch array does not need additional ESD protection structure, so the RF switch performance will not be degraded by the ESD-induced parasitic [4].

Figure 2 shows the transmission line pulse (TLP) IV curves from RF pins to ground pin on two RF switch designs in a 110 nm SOI CMOS technology. The configuration of the 1-mm-wide 32-stacked shunt branch switch array in two RF switch designs are almost identical except for their biasing resistors at G and B nodes. As can be noted from Figure 2, the biasing resistor, particularly on the gate, is an integral component of the ESD shunt mechanism. Without these resistors and the concomitant coupling, the NMOS array quickly fails when pulsed by the TLP. It also demonstrates that the self-protection function resulting from the resistor-gate capacitance coupling must be appropriately engineered to enable both the RF switching capability and the ESD switch protection. Should the gate resistor be too large, switching times will be impacted. However, reduction of the resistor value must be mitigated to provide the needed ESD protection.

Figure 2: TLP IV curves of RF pin to ground pin from two designs with different biasing resistors.

Based on the ESD protection mechanism described above, two parameters of the stacked switch array can be used to customize the ESD protection for SOI RF switch. To first order, the switch array HBM withstand voltage depends most directly on the total width of the NMOS transistor array in the stack. For most shunt switch configurations, the HBM withstand voltage is linearly related to the total NMOS array width. Furthermore, stack number has little impact on the HBM withstand voltage. However, the failure voltage (V_t2) of the switch array is directly dependent upon the switch array stack number. The switch array failure voltage (V_t2) increases when the switch array stack number increases. For some applications where the switch array is employed as a protection structure for other circuits, the switch array stack number needs to be carefully chosen to ensure that the switch array turns on at voltage lower than the breakdown voltage of circuits being protected.

The ESD protection of the switch components is primarily to protect them during assembly into the final product. While a detailed description of device and system ESD co-design is beyond the scope of this report, at the most foundational level, the system level protection must be tailored to be compatible with this on-chip protection. The system level antenna protection must be such that it will clamp the much larger, IEC 61000-4-2 type discharges. As a starting point, the system antenna protection must clamp this ESD energy at a low enough voltage so that the V_t2 of the antenna switch is not exceeded.

In summary, the series-shunt structure in SOI RF switch design has been discussed. This architecture is a unique example of a self-protecting RF circuit that has little negative impact on RF performance. The physical mechanism that provides that protection was discussed as well as several important design parameters that must be considered for optimization. Finally, the mating of the switch device ESD protection with the overall antenna system was briefly discussed.

References

1. M. B. Shifrin, P. J. Katzin, Y. Ayasli, “Monolithic FET structures for high-power control component applications”, IEEE Trans. Microw. Theory Techn., vol. 37, no. 12, pp. 2134-2141, Dec. 1989.
2. A. Tombak, M. S. Carroll, D. C. Kerr, J.-B. Pierres, E. Spears, “Design of high-order switches for multimode applications on a silicon-on-insulator technology”, IEEE Trans. Microw. Theory Techn., vol. 61, no. 10, pp. 3639-3649, Oct. 2013.
3. M. Rigato et al., “Analysis of ESD Behavior of Stacked nMOSFET RF Switches in Bulk Technology,” in IEEE Transactions on Electron Devices, vol. 65, no. 3, pp. 829-837, March 2018.
4. X. S. Wang et al., “Concurrent Design Analysis of High-Linearity SP10T Switch With 8.5 kV ESD Protection,” IEEE J. Solid-State Circuits, vol. 49, no. 9, pp. 1927–1941, Sep. 2014.