Indium-gallium-zinc-oxide (IGZO) Thin-film-transistors (TFT) and ESD
The thin-film transistor (TFT) became commercially available slightly more than 30 years ago in the form of a switch for the Liquid Crystal Display. It all started with an amorphous silicon (a-Si) TFT. Compared to the traditional crystalline silicon CMOS transistor, the a-Si TFT can be produced on large substrates and at low processing temperatures, below 300 °C, enabling integration on glass substrates and even flexible substrates.
A-Si TFTs are mainly implemented as simple pixel switches due to their low charge carrier mobility (0.5-1 cm²/Vs). An alternative semiconductor on glass substrates is low-temperature polycrystalline silicon (LTPS), outperforming a-Si TFTs by a 100x larger mobility (50-100 cm²/Vs) and often used for high-end displays and imagers. Despite the advantages, fabrication of an LTPS TFT takes more process steps, is limited in substrate size, and requires a larger process temperature. Oxide-based semiconductors as indium-gallium-zinc-oxide (IGZO) fill this gap between a-Si and LTPS nicely, exhibiting low processing temperatures and a decent charge carrier mobility of 10 up to 40 cm²/Vs [1].
Figure 1: Example cross-section of an IGZO TFT with a dual-gate fabricated on a glass substrate. The top and bottom gates can be connected by vias through the first metal layer (M1). Silicon dioxide (SiO2) is used to insulate the gates from the active IGZO layer, to achieve the field-effect transistor. After fabrication, the glass can be detached from the polyimide layer resulting in a flexible circuit.
With such characteristics, the IGZO TFTs can be used to fabricate relatively complex circuits on flexible substrates. Consequently, IGZO TFTs are evolving beyond displays and entering the fields of wearable devices and the Internet of Things (IoT). Some highlights include an ultra-flexible circuit for recording electrocardiograms [2], radiofrequency identification (RFID) tags and near-field communication (NFC) tags [1]. Even the memory field has noticed IGZO and its extremely low OFF current and recently demonstrated a capacitor-less IGZO-based DRAM cell with a retention time longer than 400 seconds [3]. We can expect the first IGZO products beyond display applications to emerge in the near future.
Figure 2: IGZO test circuits fabricated on a semi-transparent flexible substrate.
Why are IGZO-based circuits a topic of interest?
As with a large majority of products, electrostatic discharge (ESD) protection is an important concern. If we are to see IGZO products enter the fields of IoT or biomedical engineering, they will have to include ESD protection.
Perhaps ESD protection is not a great concern for wireless products, for example, NFC and RFID tags which have no wired input and output ports. Here the sensitive electronic parts will not be exposed to the user as they are electrically insulated. In this case, like for displays [4,5], a good ESD control program might be enough to protect the IGZO components during assembly. The full display will, in any case, include ESD protection circuits at the system level, even perhaps at the peripherals where the electrical connections leave the display, but not necessarily at the IGZO component level. On the other hand, some wearables like the electrocardiogram patch, might not be able to afford system-level ESD protection circuits fabricated in a different technology other than IGZO. Since the electrodes have direct contact with the end-user, they may require ESD protection circuits at the device level. The same will be true for displays and imagers if their peripheral circuits are implemented using IGZO – to enable a fully flexible display, for example.
Is ESD a concern for IGZO circuits?
Yes, like any digital or analog circuit, also IGZO TFT circuits are susceptible to ESD. Even though the IGZO TFT technology nominal voltage can be as high as 10 V, degradation and breakdown can be observed already at 20 to 30 V [6]. To avoid damage to performance, the IGZO circuit should never be exposed to voltages higher than 20 V. This means the eventual ESD protection circuits should have a clamping voltage lower than 20V, which is only twice the nominal voltage. These limits depend on the IGZO technology and could change as the technology improves.
What are the difficulties of designing ESD protection circuits in IGZO TFT?
There are several challenges when designing IGZO TFT circuits in general, but perhaps the most prominent one is the fact it is a unipolar technology. Unlike the complementary metal-oxide-semiconductor (CMOS) technology integrating two types of transistors, n-type and p-type, the IGZO TFT only provides n-type transistors. Research on p-type oxide-based TFTs to complement the IGZO n-type transistor exists. Unfortunately, the p-type transistors generally have a much lower charge carrier mobility and would make the complementary design less efficient than the unipolar one [1]. Since ESD protection circuits can rarely dictate the technology evolution, ESD protection designs will most likely have to be made with unipolar circuits too.
The second challenge of the IGZO TFT technology for ESD circuit design is that there are usually no diodes available. Even though it is possible to make diodes in the IGZO TFT technology, it also increases the process cost and is not a commodity in this industry. Therefore, the best next choice would be a diode-connected transistor. The technology options to improve the ESD performance of the diode-connected transistor would be to smartly use the back-gate or to optimize the channel material resulting in larger mobility.
Luckily, the negative threshold issue that was observed in the early IGZO TFT technology improved significantly. Therefore, the significant leakage at the zero-volt bias that would be present in IGZO TFT ESD protection circuits can be solved from the technology side.
Figure 3: Drain-to-source current as function of the gate-to-source voltage measured on a dual-gate IGZO transistor shows a positive threshold voltage (top) and leakage currents below the measurement setup noise level (bottom). These data have been measured on a 5 µm by 100 µm TFT with a drain-to-source bias voltage of 50 mV.
Nevertheless, given the limited IGZO TFT conductivity, to achieve a product-worthy ESD protection level, the ESD circuits will have to be in the millimeter or even centimeter size range [5][2]. Given the IGZO TFT technology is optimized for large areas, spending these kinds of areas for ESD protection should not be a showstopper.
Unlike the silicon integrated circuit technology, there is a very limited choice of devices in IGZO, which also limits the possible solutions of ESD protection circuits. Passive devices could help with that. Inductors, capacitors, and resistors could be used as ESD protection or to complement the active devices. A spark gap could be a compact ESD protection option too.
What about testing ESD performance of large area wearable devices?
IGZO TFT technology is a good candidate for future wearable and flexible electronic devices. If it is used in a wireless or non-contact way, consumer-side ESD protection should not be a great concern. However, if it will be used as a wearable with electrically exposed pads, it will certainly require ESD protection designs and ESD testing. In this case, the ESD testers might need to be adapted. Take the Human Body Model (HBM) ESD tester, for example. Most HBM ESD testers today target small, packaged devices in millimeter or centimeter sizes. HBM ESD testing of an IGZO TFT product might imply pins to be more than 10 cm apart. That might be challenging indeed, but perhaps some ingenious test fixtures or packaging could overcome this. Bending the flexible wearable device for ESD testing purposes could be an example.
The Transmission Line Pulse (TLP) ESD tester could be an alternative to HBM testing. Since the TLP tester is of a more academic nature than the HBM tester, it could perhaps offer more flexibility in connecting to the large IGZO circuit. Even though the TLP is a 50-Ohm tester while HBM has a typical series resistance of 1500 Ohm, we have observed comparable ESD testing results with both testers [6]. Since there is no universal conversion rule, care needs to be taken when interpreting TLP measurement results as HBM protection values.
Acknowledgments
This article has been written with the help of Kris Myny, Shih-Hung Chen, Hikmet Celiker, and Nikolas Papadopoulos from imec, Belgium.
This work received funding from the European Research Council under the European Union’s Horizon 2020 research and innovation program under grant agreement no. 716426 (FLICs project).
This work was financed by the Flexlines project within the Interreg V-program Flanders-The Netherlands, a cross-border cooperation program with financial support from the European Regional Development Fund, and co-financed by the Province of Noord-Brabant, The Netherlands.
References
- K. Myny, “The development of flexible integrated circuits based on thin-film transistors,” Nature Electronics, vol. 1, no. 1, p. 30, 2018.
- M. Sugiyama, T. Uemura, M. Kondo, M. Akiyama, N. Namba, S. Yoshimoto, Y. Noda, T. Araki, and T. Sekitani, “An ultraflexible organic differential amplifier for recording electrocardiograms,” Nature Electronics, vol. 2, no. 8, pp. 351–360, 2019.
- A. Belmonte, H. Oh, N. Rassoul, G. L. Donadio, J. Mitard, H. Dekkers, R. Delhougne, S. Subhechha, A. Chasin, M. J. van Setten, L. Kljucar, M. Mao, H. Puliyalil, M. Pak, L. Teugels, D. Tsvetanova, K. Banerjee, L. Souriau, Z. Tokei, L. Goux, and G. S. Kar, “Capacitor-less, Long-Retention (>400s) DRAM Cell Paving the Way towards Low-Power and High-Density Monolithic 3D DRAM,” in 2020 IEEE International Electron Devices Meeting (IEDM), 2020, pp. 28.2.1–28.2.4.
- ESD Association, “ESD TR21.0-01-18 Technical Report for Challenges in Controlling ESD in the Manufacturing of Flat Panel Display,” 2018.
- Joshua (Yong Hoon) Yoo, “ESD Issues for Flat Panel Displays”, In Compliance Magazine, February 2021.
- M. Simicic, N. R. M. Ashif, G. Hellings, S.-H. Chen, M. Nag, A. J. Kronemeijer, K. Myny, and D. Linten, “Electrostatic discharge robustness of amorphous indium-gallium-zinc-oxide thin-film transistors,” Microelectronics Reliability, vol. 108, p. 113632, 2020.
About The Author
