The Transistor: An Indispensable ESD Protection Device – Part 2

The invention of the bipolar transistor and later the MOS transistor evolution into wide applications for ESD protection in the semiconductor technologies was previously published in the January 2023 issue of this magazine. In this second and final part of the article we discuss the MOS transistor in the role of ESD protection for high-voltage applications and take a look into a possible future of ESD protection devices for high-performance computing applications.

Using MOS Transistors as ESD Protection Clamps in high voltageTechnologies

Typically, when we speak about high voltage technologies, we refer to integrated circuits having pins with voltage rating higher than 10V. These technologies combine different elements: digital and analog signals processing are managed together with Power transistors. In this way it is possible to provide high voltage and high current to the loads. Some typical examples of possible applications are power control and conversion circuits, power drivers, automotive applications, and sensors or actuators driving circuits. Anyway, the list may be easily extended to many more cases.

High voltage technologies show some specific characteristics, which make them unique. First of all, the ESD design window is narrower and narrower. Especially for high voltage components, such as devices rated above 40V, the ESD window actually tends to vanish completely. So, it is challenging to have the right space to allow snapback-based ESD protections. Moreover, the high clamping voltage requires a normally large device, with a remarkable area occupation. Then, we need to consider that typical high voltage components are potentially weak and ballasting is not so effective as for CMOS technologies. Finally, these technologies are showing several implants with a large number of parasitic transistors, both NPN and PNP. So, Latch-up risk is a serious threat.

Bipolar-based ESD solutions are widely used in HV Technologies, but several approaches can be adopted, taking into account the specific needs of the applications to be addressed and the device portfolio available in the different technologies. One relatively simple approach implies the usage of several Low Voltage ESD protections (such as for example series of grounded gate NMOS or GGNMOS devices). As reported in Figure 1, stacking a suitable number of elementary components, higher trigger and holding voltage levels can be reached. The exact number of the protections can be defined based on the application voltage requirements. The main drawback of this solution is that triggering and holding voltages cannot be independently modulated, but they will be a multiple of the initial value. Precise tuning of these values in case of narrow ESD windows can be therefore a very challenging task.

Figure 1: 100ns-TLP characterization of LV GGNMOS in series

Alternatively, the parasitic NPN embedded in HV‑NMOS devices (Drain/Body/Source) can be also adopted as ESD protection. In this case the voltage capability is guaranteed by the original MOS device, which is designed to sustain high voltagein off-state. The main issue related to this type of component is that they are quite fragile in snapback-mode, due to a large instability of the triggering mechanism inducing a premature filamentation and eventually permanent damage at relatively low current levels. Several techniques were reported in the past to improve the overall robustness of HV-NPN ESD protections, such as the usage of dedicated deep implants [8], a dedicated layout implementation to modulated the body resistance [9], and also the addition of dedicated triggering circuits, directly embedded into HV transistor to turn on the bipolar action in a controlled way [10].

Finally, bipolar protections in HV technologies may be also implemented using PNP devices. This is a rather common approach, especially for safety-critical applications where no snapback-based protections are allowed due to their Latch-up sensitivity. The main advantages of PNP protections are the almost complete absence of snapback effects (see Figure 2), the fact that these do not require any ballasting to get a uniform current flow, and their layout-friendliness as matrix-based layout are easily implementable.

Figure 2: 100ns-TLP characterization of PNP-ESD arrays

ESD Protection in FinFET Technologies and Beyond

We observe two main scaling trends driving CMOS technology advancement today. The first trend is about continuing the Moore’s Law of shrinking the transistor and increasing its performance – part of the design-technology co-optimization methodology or DTCO for short. The second trend is about packaging chips and chiplets together into a single system – part of the more recent system-technology-co‑optimization methodology or STCO for short. 

To increase performance, the DTCO trend is pushing the transistor evolution towards the gate-all-around type of architecture, like the nanosheet transistor. This enables stronger channel control and therefore better performance in terms of a digital circuit design – lower power consumption and faster response. With this evolution, most if not all the transistor current will flow through a channel surrounded by the gate. The substrate silicon is not truly needed for the digital circuit, so it becomes a parasitic channel. With this, the parasitic bipolar transistor that is very useful in ESD protection designs becomes a secondary effect – a parasitic effect of a parasitic channel. 

The furthest concept on this roadmap is the CFET [1]. Here the n-FET is completely isolated from the substrate silicon. Only the p-FET remains in contact with the substrate. Therefore, it becomes impossible to form the parasitic bipolar transistor. This is indeed good news for the designers who worry about the unwanted latch-up effect. Unfortunately, the ESD protection designers might feel quite the opposite. The impact of technology scaling on the ESD protection designs has been described in a more detailed way in [2].

However, the future is not so dark for the ESD protection designers. The roadmap in Figure 3 is for the core transistor, but we also have the thick-oxide input-output (I/O) transistor (not shown in the figure). Naturally, the IO devices also must follow the core transistor roadmap as they use the same fabrication process. However, they usually need a few different steps, for example, to form the thicker gate dielectric. For the nanosheet FET this difference might be to skip the etch step that releases the nanosheets and use the superlattice finFET as the I/O device instead (described for a nanowire device in [4]). This enables better contact to the substrate silicon and therefore brings the parasitic bipolar effect back to the front seat. 

Figure 3: The imec tentative device scaling roadmap beyond the 5 nm node following the design-technology co-optimization (DTCO) trend – from FinFET to CFET. The buried power rail (BPR) is a performance booster enabling further scaling [3]. Note that from the nanosheet FET onwards, the main FET channel is physically separated from the silicon substrate.

STCO (system-technology-co-optimization), on the other hand, looks at integrated circuit technology more from a perspective of 2.5D and 3D chip integration. Compared to DTCO where the device itself is scaled down, in STCO the chip interconnect pads are scaled. That enables bonding of chips fabricated in different technologies into a single package or system. Basically, we are looking at a system of deconstructed chips (chiplets), each fabricated with a process optimized for their function, for example memory, logic, analog or even optical communication. No matter the option from the STCO roadmap, they have a common trend: substrate thinning, which can reach extreme dimensions down to 500 nm [5]. This thinning is the focus point for our story on the system-technology-co-optimization methodology (STCE) scaling trend and the bipolar transistor.

Thinning down the semiconductor substrate until it reaches the p-wells and n-wells will reduce the current gain of the bipolar transistor. The well depth depends on the used technology, of course. Still the bottom of the implant well can be reached and the effects on the bipolar transistor can be measured [6] for wafer thicknesses of 500 nm and below. This is good news for avoiding the unwanted latch-up effect, but perhaps not the best news for ESD protection circuits.

Figure 4: Product of the npn and pnp current gain values – thyristor (pnpn) beta product – as function of wafer thickness and spacing between the thyristor anode and cathode. When the beta product is below 1, latch-up becomes self-extinguishing.

Like for the device scaling trends, wafer thinning at first might seem like an issue for ESD protection designers. However, new technologies also bring new opportunities. One of these opportunities is presented by through-silicon-vias directly contacting the buried power rail and thus enabling the backside power delivery network. Thanks to this backside metallization, backside active contacts can be created, at the cost of extra process steps. This enables us to form vertical junction devices [7].

It should be highlighted, a vertical bipolar transistor can be made with one or two electrodes in the usual frontside together with the MOSFETs and the remaining electrodes on the backside of the wafer with the backside metal layers. Such a vertical bipolar transistor might indeed be an interesting opportunity for ESD protection designers.

Figure 5: Sketch of a integrated circuit cross-section depicting a possible way to fabricate vertical diodes and bipolar transistors in advanced technologies. The core devices are finFETs. The buried power rail (BPR) connects to the back side metallization by nano-TSVs (through-silicon vias). Active backside contacts have been demonstrated in [7].

Summary

The bipolar transistor was invented 75 years ago and it is still widely used in many different applications and technology nodes. As shown in the two parts of this article, it is representing one of the most common elements to realize an effective and robust ESD protection network in advanced CMOS, in RF in high voltage and in finFET technologies, with a large variety of different flavors and implementations. 

References

1. S. Subramanian et al., “First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers,” 2020 IEEE Symposium on VLSI Technology, pp. 1-2.
2. Shih-Hung Chen, “Next to FinFET, How Will ESD Suffer?”, In Compliance Magazine, July 2021. 
3. J. Ryckaert et al., “Enabling Sub-5nm CMOS Technology Scaling Thinner and Taller!” 2019 IEEE International Electron Devices Meeting (IEDM), pp. 29.4.1-29.4.4.
4. G. Hellings et al., “Si/SiGe superlattice I/O finFETs in a vertically-stacked Gate-All-Around horizontal Nanowire Technology,” 2018 IEEE Symposium on VLSI Technology, pp. 85‑86.
5. G. Van der Plas, E. Beyne, “Design and Technology Solutions for 3D Integrated High Performance Systems,” 2021 Symposium on VLSI Circuits.
6. K. Serbulova et al., “Impact of Sub-µm Wafer Thinning on Latch-up Risk in STCO Scaling Era,” 2021 43rd Annual EOS/ESD Symposium (EOS/ESD), pp. 1-6.
7. K. Serbulova et al., “Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO,” 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), pp. 431-432.
8. T. H. Lai et al., “Design of Modified ESD Protection Structure with Low-Trigger and High-Holding Voltage in Embedded High-Voltage CMOS Process,” IRPS Proc., 2011, pp. 392-395.
9. J. H Lee et al., “The Influence of The Layout On The ESD Performance Of HV-LDMOS,” ISPSD Proc., 2010, pp. 303-306.
10. W. Y. Chen et al., “Improvement on ESD Robustness of Lateral DMOS in High-Voltage CMOS ICs by Body Current Injection,” ISCAS Proc., 2009, pp. 385-38.