Understanding Embedded On-Chip ESD Detection, Part 1

Article, Blog Post
November 1, 2023
Understanding Embedded On-Chip ESD Detection, Part 1

© 2019 Jeffrey C. Dunnihoo

Introduction

Electrostatic Discharge (ESD) poses a significant threat to the reliability and longevity of electronic devices. As integrated circuits (ICs) continue to shrink in size and increase in complexity, they become more susceptible to ESD damage in the factory and soft-errors and upsets in the field, especially wearable and medical devices.1 (See Figure 1.)

Figure 1: In Compliance 2021 – Advances in CMOS Technologies Leading to Lower CDM Target Levels

Merely “increasing” ESD protection won’t solve all of these problems going forward and may even make some worse. In this 3-part series, we will introduce the growing challenges of soft-upsets and latent ESD damage and outline the benefits of embedded ESD detection as a solution to this problem.

Chip-level ESD designers have been in an arms race to achieve lower clamping voltages and higher clamping currents to prevent factory returns and failure analysis costs for the chip vendor.

Unfortunately, solving the factory equation in isolation creates other headaches for system designers, including more ESD upsets and soft-errors and more constraints in TVS protection selection.

ESD “event detectors” have been used for years in factory environments to identify and remediate ESD discharges during manufacturing. Now design engineers are embedding system-level and on-chip ESD detection technologies into their systems to analyze and recover from both factory and field ESD events.

The Need for Embedded ESD Detection

Complexity of Advanced Integrated Circuits

Over the years, there has been a relentless drive toward smaller, faster, and more power-efficient integrated circuits. This drive has led to the development of advanced semiconductor process nodes with smaller feature sizes, allowing for greater numbers of transistors to be packed onto a single chip. However, this miniaturization comes with a significant downside: increased sensitivity to ESD events.2 (See Figure 1.)

As ICs technology nodes become smaller, gate oxides become thinner, metallization narrower, and cross-domain voltage clamping becomes more challenging, ever smaller and smaller electrostatic discharges can now cause catastrophic damage to an IC. Moreover, even the clamped pulses that are survivable can wreak havoc on the system state and coherency and cause soft-errors, upsets, and data loss.

Vulnerability of Modern ICs to ESD Damage and Upset

ESD damage can manifest in various ways, from immediate and catastrophic failures to latent defects that only surface after the device has been in use for some time. Such damage can result in costly warranty claims, recalls, and a tarnished brand reputation for manufacturers.

For the system to pass successfully, it is essential that both the system-level TVS protection and chip-level protection work together effectively to achieve the target system stress levels. The ESD Industry Council introduced the System Efficient ESD Method (SEED) to address this.3 Pragma Design has implemented the free PESTO analysis tool to help test different protection devices and devices to be protected. But due to soft-upsets, just because the system merely survives does not mean it will pass qualification!

Figure 2: Interactions of I/V characteristics in a “System Efficient ESD Design” (SEED)

Let’s consider four distinct scenarios shown in Figure 2:

  1. Desired Operation: If the system‑level ESD Protection activates and restricts the voltage below the chip-level protection’s triggering point, minimal current enters the chip.
  2. Inadequate TVS Design: Here, the system-level ESD Protection activates, but it restricts the voltage just above the chip-level protection’s failure threshold, rendering the chip-level protection ineffective. This mismatch can put the chip’s integrity at risk, emphasizing the need for well-matched protection mechanisms between system-level and chip-level components.
  3. Overzealous IC Design Leading to Self-Destruction: When chip-level protection is “too good” and triggers and prevents the system-level TVS protection from activation, it results in the chip-level protection clamping the entire event. While the robustness of chip-level protection is very good for HBM or CDM pulses, it may still prove insufficient to handle the full system ESD event, leading to a design failure.
  4. Overzealous IC Design Causing Soft Errors and Upsets: If the chip-level device protection circuit triggers in a way that disrupts VDD-to-VSS voltage, causing a reset or other cross-domain power sequencing issues without causing damage, the system may survive the ESD strike but lose data and functional coherency. In this case, while the on-chip protection may be effective in reducing F/A returns from factory damage, it can also increase the system’s susceptibility to glitches and near-field coupled pulses.

Given these growing challenges, there is a growing need for embedded ESD detection solutions that can detect and respond to ESD events that may otherwise be incurable.

Embedded Detection Technology

Pragma Design and Certus Semiconductor have introduced real-time, on-chip ESD detection I/O cell design and characterization for standard and custom processes, and many OEM semiconductor manufacturers have also invested in (and incorporated into their design flow) on-chip ESD technology in their products. Unfortunately, as an internal design tool, it may not be advertised in the product specifications. Even though it may be undocumented, ask your chip vendor if they already have or can provide this feature. It can help them with failure analysis, and it can help the system designer optimize their ESD protection budget.4

How Embedded Detection Works

Embedded detection technology can be appended to a system, but ideally, it is designed directly into integrated circuits during the chip design phase. It works by recording ESD detection events at all or selected I/O pads and power pins. (See Figure 3.) When an event is detected, embedded detection can respond in various ways, such as triggering protective measures, logging event data, or providing feedback to the device’s operating system.

Figure 3: I/O Cell Block diagram with ESD Detection (Green)

Key components and functionalities of embedded detection technology include:

  1. Detectors: Embedded detection includes specialized ESD sensors distributed strategically among the chips I/O cells. These sensors are designed to detect electrostatic discharge events and record the events so that they can be read back from registers or via JTAG.
  2. Real-Time Monitoring: Embedded detection continuously monitors the state of the chip in real-time, and can create software interrupts and logic resets as needed.
  3. Event Classification: When an ESD event is detected, embedded detection can characterize it by location and effective external threat level.
  4. Response Mechanisms: Embedded detection can be configured to trigger specific responses to detected events. For example, it can disable affected circuits, redirect signals, or reset components to prevent damage.
  5. Data Logging: Embedded detection can log event data, allowing designers and manufacturers to analyze and diagnose ESD events that occur during the device’s lifetime.

Benefits of Using Embedded Detection

The integration of embedded detection technology into IC designs offers several advantages:

  1. Real-Time Protection: Embedded detection provides real-time protection against ESD events, reducing the impact of soft-errors and upsets.
  2. Improved Reliability: By responding to ESD events proactively, embedded detection enhances the reliability and lifespan of electronic devices.
  3. Lower Manufacturing Costs: Embedded detection reduces the uncertainty of external threats, and can help optimize external protection components, resulting in cost savings during manufacturing.
  4. Performance Optimization: Embedded detection can be used to optimize the performance of ICs by allowing them to continue operating in the presence of ESD events that would otherwise cause shutdown.
  5. Data Analytics: The data logged by embedded detection can be invaluable for diagnosing and mitigating ESD-related issues during product development and in the field.

Conclusion

In Part 1 of this article series, we’ve explored the critical need for embedded on-chip and system-level ESD detection in the context of modern integrated circuits. The vulnerabilities of advanced ICs to ESD damage have necessitated the development of innovative solutions like embedded detection technology. Embedded detection’s real-time monitoring and response capabilities offer a new level of protection and reliability to electronic devices.

In Parts 2 and 3, we will consider the practical aspects of implementing embedded ESD detection and provide guidance on integrating these technologies into semiconductor and system designs and ensuring the robustness of their electronic devices.

Endnotes

  1. M. Kohani and M. Pecht, “Malfunctions of Medical Devices Due to Electrostatic Occurrences Big Data Analysis of 10 Years of the FDA’s Reports,” IEEE Access, vol. 6, pp. 5805-5811, 2018, doi: 10.1109/ACCESS.2017.2782088.
  2. EOS/ESD Association, Inc., “Advances in CMOS Technologies Leading to Lower CDM Target Levels,” In Compliance Magazine, April 2021.
  3. White Paper 3 System Level ESD Part II: Implementation of Effective ESD Robust Designs (v2.0 March 2019). 
  4. https://certus-semi.com/certus-semiconductor-partners-with-pragma-design-for-embedded-esd-detection-technology