Use of HBM and CDM Layout Simulation Tools
Why is the Use of these ESD Layout Simulation Tools Necessary?
Electronic Design Automation (EDA) ESD verification tools have become instrumental to the design and verification flow of integrated circuits (IC’s). This trend has been mostly driven by the extraordinary development and increasing complexity/technology scaling of IC’s in the past few years. Furthermore, increasingly demanding product performance with necessary ESD reliability requirements makes it very challenging to achieve first-time-right silicon for both functional and ESD performance. In that context, the use of ESD verification tools to de-risk IC designs before tape-out or for debugging purposes has become critical. In this article, the methodology of the state of the art of HBM and CDM layout simulations tools is described. Two real-life case studies are presented briefly and the outlook towards future developments is discussed.
Methodology of the ESD Simulation Tools
The simulations are typically performed at top-level IC design. Figure 1 describes a simplified simulation flow of the HBM and CDM layout check tools. The design input used is a post-LVS (layout versus schematic) database. In addition, the ESD device characteristics are required and integrated as piecewise linear (PWL) or SPICE models. Also, technology files containing process information related to devices layers and metallization stack, typically from the process development kit (PDK) are included in the simulation setup. Finally, the backend ESD current density rules, gate oxide, and drain-source breakdown voltage stress are added as inputs to the ESD solver. Note that both ESD and victim devices characteristics are determined by means of transmission line pulse (TLP) and/or very fast (VF)-TLP characterizations. The main outputs from the ESD simulator are the ESD current density, gate stress limit violations, drain-source stress violations, and the overall ESD zaps results.
Figure 1: A simplified simulation flow of the HBM and CDM layout check tools.
Description of the ESD Layout Check Tools
The ESD layout check tools verify using HBM and CDM model source stimuli. The HBM check verifies that ESD design guidelines are fulfilled and met at full-chip level by performing pad-to-pad simulations. In addition, it highlights weak areas of the design, reports current density (CD) violations, and paths with high point-to-point (P2P) resistance. The CDM check is run to identify and localize overstressed gate oxide and drain-source of MOS devices due to CDM stress. Individual pin CDM stress discharge currents are simulated for all IC pins. A predictive CDM SPICE circuit simulation method based on the tester, package, and full IC modeling approach is presented in Figure 2 where the RLC network is extracted using the Time Domain Reflectometry (TDR) method [1]. This type of tool is especially useful in checking the VGS voltages of internal core NMOS and PMOS receivers of intra- or cross-power ground domain and comparing the values to their gate oxide breakdown voltages.
Figure 2: SPICE Model of the CDM Discharge Setup including the CDM Tester and PUT Parasitics [2].
ESD Layout Simulation Prerequisites
The main required technology files for ESD layout simulation are the interconnect technology describing the backend layer stack and the layer setup or mapping file. The ESD devices or protection circuits are either SPICE simulated or described as PWL models extracted from TLP and/or VF TLP data. The ESD RC-clamps are directly simulated using the SPICE model. The other types of clamps and ESD devices are essentially PWL modeled, this includes but is not limited to ESD diodes, silicon controlled rectifiers (SCR’s), grounded gate NMOS (ggNMOS), gate coupled PMOS (gcPMOS) transistors, and vertical latch-back NPN and PNP bipolar transistors. Further ESD characterizations are also required on the backend metal stack structures with the purpose to determine the ESD robustness of the metal interconnects and vias under ESD phenomena. Separate HBM and CDM time-domain current density rules are derived from those data.
Examples of ESD Simulations
As an illustration, the use of ESD simulation check tools is demonstrated for two case studies, one on a complex RF product and the second on a mixed-signal integrated circuit. The ESD simulation tools were used in these cases to verify the implemented ESD fixes before tape out of IC design revisions, and the ESD qualification results of the new silicon in each case confirmed the passing of the ESD requirements for those devices.
Figure 3 and Figure 4 show 2kV HBM simulations and 500V CDM simulations results of those IC’s respectively. The simulation results fully correlate with the actual failure mechanism observed in both the RF (Figure 3) and the mixed-signal (Figure 4) IC’s. Also, a very good correlation is found between the CDM simulation and measured CDM waveforms from the JS-002 verification modules. These modules correspond to the so-called ESDA small “coin” (with a capacitance of about 4.0pF) and large “coin” (with a capacitance of about 30.0pF). They both make use of the FR-4 material.
Figure 3: HBM Simulations of an RF Product reproducing a 2kV HBM Failure Mechanism [3].
Figure 4: CDM Simulations of a mixed-signal product reproducing the 500V CDM failure mechanism [3]. Simulated and measured CDM waveforms from the JS-002 verification modules are also shown.
Conclusion and Outlook
This article has demonstrated the usage and benefits of HBM and CDM ESD layout simulations tools. The ESD layout simulation procedure typically consists of several steps. The benefits include the detection of risky ESD configurations and sites, the identification of ESD failure mechanisms, and the verification of the proper implementation of the overall ESD protection strategy of the IC design. The ESD layout check tools are typically silicon calibrated and integrated into the ESD design flow to catch ESD risks prior to tape-out. Further developments are expected in the mixed-mode ESD simulations combining TCAD and transient SPICE simulations to improve the predictability of the ESD robustness of integrated circuits.
References
- D.A. Smolyansky, “TDR Techniques for Characterization and Modeling of Electronic Packaging,” High-Density Interconnect Magazine, 2 parts (TDA Systems, Application Note PKGM-0101), March and April 2001.
- Dolphin Abessolo-Bidzo et al., “CDM Simulation Based on Tester, Package and Full Integrated Circuit Modeling: Case Study,” IEEE Trans. on Electron Devices, vol. 59, pp. 2869 – 2875, November 2012.
- Dolphin Abessolo-Bidzo et al., “A Study of HBM and CDM Layout Simulations Tools,” Electrical Overstress/Electrostatic Discharge Symposium Proceedings, paper 5B.2, 2018.
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