SR792024 SEARCH and RETRIEVAL INDEX to EOS/ESD SYMPOSIUM PROCEEDINGS 1979 to 2024 (A GUIDE TO THE KNOWLEDGE BASE OF THE EOS/ESD SYMPOSIUM PROCEEDINGS) Published by (26 ESD ASSOCIATION ,1&
Abstracting is permitted with credit to the source. Instructors are permitted to photocopy portions for noncommercial classroom use. For other copying, reprint or reproduction, write to EOS/ESD Association, Inc., 218 West Court Street, Rome, NY 13440 Copyright © 2024 by EOS/ESD Association, Inc.
TABLE OF CONTENTS INTRODUCTION SECTION 1: AUTHOR INDEX SECTION 2: PAPER AWARDS SECTION 3: CHRONOLOGICAL CITATIONS OF PAPERS
Web link to (26 ESD Association ,QF Home page http://www.esda.org
INTRODUCTION The EOS/ESD Symposium annual proceedings are a major source of information on electrostatic discharge. The proceedings also cover electrical overstress in general and, to a lesser extent, EMI. The first symposium was held in 1979 in Denver, Colorado. It was sponsored by ITT Research Institute and managed by a Steering Committee of individuals from industry and government organizations interested in EOS/ESD. The Symposium has been held every year since 1979. In 1983 EOS/ESD Association ,QF became a cosponsor with IITRI until 1989. Starting in 1990 the EOS/ESD Symposium became sponsored by the EOS/ESD Association in cooperation with the IEEE Electron Devices Society. ,Q ESD Association expanded its area of interest to non-electronic concerns of ESD and started to be known as the (26 ESD Association ,QF. The symposium started to publish a few papers from other fields. Paper number references for this index consist of 5 digit numbers. The first two digits are the proceeding’s year where the paper can be found. The last three digits are the proceedings page number on which the paper starts RU WKH DVVLJQHG SDSHU QXPEHU. proceeding’s year 97298 starting page number There are some workshop reports and summaries at the back of the proceedings. The workshop information was not included in this index. Starting in 1991 the proceedings was handed out at the Symposium. This is discernible by the paper awards photographs, since the awards for 1989 appear in both the 1990 and 1991 proceedings. So before 1991, to look at award photos for papers given a certain year you looked in the next year’s proceedings. For the awards from 1990 on, you look in the second year’s proceedings after the paper was given.
SECTION 1 AUTHOR INDEX
Abderhaiden, J. 90143 An Analysis of Low Voltage ESD Damage in Advanced CMOS Processes Abessolo-Bidzo, D. 2011163 Predictive CDM Simulation Approach Based on Tester, Package and Full Integrated Circuit Modeling 2013283 ESD Protection Circuit for a Sub-1 dB Noise Figure LNA in a SiGe:C BiCMOS Technology 20154A1 A Study of the Effect of Remote CDM Clamps in Integrated Circuits 20158A1 Wear out Effects in ESD Characterization and Testing 20172A3 Circuit under Pad Active Bipolar ESD Clamp for RF Applications 20172B1 Window Effects in HBM and TLP Testing 20185B2 A Study of HBM and CDM Layout Simulations Tools 20201B3 Charged Device Model (CDM) and Capacitive Coupled Transmission Line Pulsing (CC-TLP) Stress Severity Study on RF 20214A1 A Silicon BJT Active ESD Clamp Design in a Silicon Germanium HBT BiCMOS Technology Abou-Khalil, M.J. 2007028 Design Optimization of Gate-Silicided ESD NMOSFETs in a 45nm bulk CMOS Technology 2007385 Process and Design Optimization of a Protection Scheme Based on NMOSFETs with ESD Implant in 65nm and 45nm CMOS Technologies 2008228 Capacitance Investigation of Diode and GGNMOS for ESD Protection of High Frequency Circuits in 45nm SOI CMOS Technologies 2008304 Investigation of ESD Performance of Silicide-Blocked Stacked NMOSFETs in a 45nm Bulk CMOS Technology 2008312 ESD Protection Using Grounded Gate, Gate Non-Silicided (GG-GNS) ESD NFETs in 45nm SOI Technology 2009334 Investigation of Voltage Overshoots in Diode Triggered Silicon Controlled Rectifiers (DTSCRs) Under Very Fast Transmission Line Pulsing (VFTLP) Absil, P. 20243A1 ESD Robustness of Germanium Photodetectors in Advanced Silicon Photonics Technology Aburano, R. 2005178 Partitioned HBM Test – A New Method to Perform HBM Tests on Complex Devices Acevedo, M. 2001262 The Purity, Wetting, and Electrical Properties of Static-Dissipative Surfactant Coatings Versus Inherently-Dissipative Polymer Alloys Acharya, D. 20206A5 Slow Turn Off Optimization of CMOS ESD NAND Clamp Design to Eliminate Fly-Back Damage During Unlatch Adams, C.S. 87028 Thermoplastic Composites for ESD Protection Adams, J. 2012191 Test Method Recommendations for the Evaluation of Packaging Materials Used for Small Static Sensitive Electronic Components Adams, O.E. 81151 EOS/ESD Failure Threshold Analysis Errors, Their Source, Size and Control 82019 Limitations in Modeling Electrical Overstress Failure in Semiconductor Devices 88053 Photoemission Testing for ESD Failures Advantages and Limitations Adkisson, J.W. 96101 Linewidth Control Effects on MOSFET ESD Robustness Adriano, C. 2000060 Detecting ESD Events using a Loop Antenna Adris, M-F. 2012129 Implementing Air Ionizing Blower at KLA Tencor 2401 Metrology Tool Reduce Visual Inspection Failure for Semiconductor Wafers
Agarwal, D. 20159A2 EOS Characterization Methodology Applied to Disable Feature of ESD Power Clamps Agarwal, R. 20156A2 A New Full-Chip Verification Methodology to Prevent CDM Oxide Failures Agha, J. 2008094 Single Pulse CDM Testing and its Relevance to IC Reliability Agneray, A. 2003161 A Physical Model to Explain Electrostatic Charging in an Automotive Environment; Correlation with Experimental Approach Aharoni, E. 20165B1 Empirical ESD Simulation Flow for ESD Protection Circuits Based on Snapback Devices 20174A4 Empirical ESD Models for Cascode ESD Transistors 20202A2 Empirical ESD Modeling of Multi-Gate ESD Transistors Ahmed, T. 20235A3 A Hybrid Finite Difference Model for Open Base Transistors with Kirk Effect Aidam, M. 95095 Calculation and Measurement of Transient Fields of Voluminous Objects 95101 To What Extent Do Contact-Mode and Indirect ESD Test Methods Reproduce Reality? 96203 Numerical Calculation of ESD Ainsworth, G.F. 88195 Hood Ionization in Semiconductor Wafer Processing: An Evaluation Akers, M.D. 2001082 Modular, Portable, and Easily Simulated ESD Protection Networks for Advanced CMOS Technologies 2003017 Boosted and Distributed Rail Clamp Networks for ESD Protection in Advanced CMOS Technologies Akram, A. S. 2008235 ESD Device Design Strategy for High Speed I/O in 45nm SOI Technology Akrout, Y. 2009091 CDM Protection Design for CMOS Applications Using RC-Triggered Rail Clamps Alanzo, A. 2000111 TLP Measurements for Verification of ESD Protection Device Response Albano, T. 99168 Test Methodologies for Detecting ESD Events in Automated Processing Equipment Alexander, D.R. 80059 Failure Threshold Distributions in Bipolar Transistors 81114 Electrical Overstress Investigations in Modern Integrated Circuit Technologies Alexander, P.H. 97107 Fast Fourier Transform Analysis of Published ESD Waveforms and Narrowband Frequency Domain Measurement of Human ESD Events Ali, M.Y. 20154B2 ESD Protection of Open-Drain I²C using Fragile Devices in Embedded Systems 20176B3 A Novel, SCR-Based, Distributed Power Supply ESD Network for Advanced CMOS Technologies Aliaj, B. 2009204 2.5-Dimensional Simulation for Analyzing Power Arrays Subject to ESD Stresses 2010301 Study of Power Arrays in ESD Operation Regimes 2014342 Overcoming Multi Finger Turn-on in HV DIACs Using Local Poly-Ballasting 20154A3 Active Clamps with Hybrid BJT-CMOS Operation Mode
Alian, A. 20214A3 ESD Failures of GaN-on-Si D-Mode AlGaN/GaN MIS-HEMT and HEMT Devices for 5G Telecommunications Allard, B. 20159A2 EOS Characterization Methodology Applied to Disable Feature of ESD Power Clamps 20165B2 An Automated Tool for Chip-Scale ESD Network Exploration and Verification Allen, J. 2001044 An Analysis of ESD Packaging Systems Through Thermoforming Almazar, R. 95118 Sporadic Effect of Leadscan Machine To CMOS ESD Low Yielding Lots 96110 Immediate Elimination of Gross ESD Failures in PLCC MECL Product Line Through Innovative Techniques Almeras, C. 20184B5 An ESD Case Study of Defect Analysis in High Speed Electronics Manufacturing Alvarez, D. 2005413 PMOSFET-based ESD Protection in 65nm Bulk CMOS Technology for Improved External Latch-up Robustness 2007028 Design Optimization of Gate-Silicided ESD NMOSFETs in a 45nm bulk CMOS Technology 2007328 Reliability Aspects of Gate Oxide under ESD Pulse Stress 2007385 Process and Design Optimization of a Protection Scheme Based on NMOSFETs with ESD Implant in 65nm and 45nm CMOS Technologies 2008304 Investigation of ESD Performance of Silicide-Blocked Stacked NMOSFETs in a 45nm Bulk CMOS Technology 2013174 Optimized Netlist Checks – Full Chip ESD Verification 2013305 CDM Single Power Domain Failures in 90 nm 20153A1 Essential – Integration of ESD Verification Methodologies 20153B3 ESD Failure Caused by Parasitic SCR in an Overvoltage Tolerant I/O 20173B4 Influence of Self-Heating on ESD Current Distribution in Metal Lines Alves, S. 2004174 ESD Induced Latent Defects in CMOS ICs and Reliability Impact Amarnath, J. 2011230 Movement of Metallic Particles in a 3-Phase Common Enclosure Gas Insulated Substations Amato, M. 20243A3 Bidirectional DIAC Devices with Two-Stage Triggering Amerasekera, A. 86208 ESD Pulse and Continuous Voltage Breakdown in MOS Capacitor Structures 90119 Standard ESD Testing of Integrated Circuits 90143 An Analysis of Low Voltage ESD Damage in Advanced CMOS Processes 92265 An Investigation of BiCMOS ESD Protection Circuit Elements and Applications in Submicron Technologies 94237 The Impact of Technology Scaling On ESD Robustness and Protection Circuit Design [BPP] 95162 Advanced CMOS Protection Device Trigger Mechanisms During CDM [BPR] 96285 EOS/ESD Analysis of High-Density Logic Chips 97230 Design Methodology for Optimizing Gate Driven ESD Protection Circuits in Submicron CMOS Processes 98161 ESD-Related Process Effects in Mixed-Voltage Sub-0.5 µm Technologies 2001071 Modeling Substrate Diodes under Ultra High ESD Injection Conditions Ames, S. 2002092 Test Methods, Test Techniques, and Failure Criteria for Evaluation of ESD Degradation of Analog and Radio Frequency (RF) Technology Ammer, M. 20174A3 How to Build a Generic Model of Complete ICs for System ESD and Electrical Stress Simulation 20183A3 Predicting System Level ESD Robustness Using a Comprehensive Modelling Approach 20188A2 Modeling the Transient Behavior of MOS-Transistors during ESD and Disturbance Pulses in a System with a Generic Black Box Approach
20195A1 Application Example of a Novel Methodology to Generate IC Models for System ESD and Electrical Stress Simulation out of the Design Data 20195A3 Characterizing and Modeling Common Mode Inductors at High Current Levels for System ESD Simulations 20231A3 Novel ESD Characterization Method for Bipolar Devices Using a Combined TLP System with Dynamic Base Bias 20235A2 A Versatile Behavioral Snapback ESD Model Incorporating Transient Effects and Failure Detection Amoruso, V. 99335 An Improved Model of Man for ESD Applications Amos, C.T. 85163 A Technique for Real Time Examination of Sub-System ESD/EOS Damage in Integrated Circuits [BPR] 86219 A Study of EOS in Microcircuits Using the Infra-Red Microscope Anaf, L.J. 93177 Selecting Materials for Protection Against ESD Using an ESD Shielding Effectiveness Meter Anand, Y. 79097 Electrostatic Failure of X-Band Silicon Schottky Barrier Diodes 93103 Electrostatic Failure of GaAs Planar Doped Barrier Diodes 99160 Latent ESD Failures in Schottky Barrier Diodes 2000387 Random GaAs IC’s ESD Failures Caused by RF Test Handler Anderson Jr., W.T. 87205 Electrostatic Discharge Effects in GaAs FETs and MODFETS Anderson, B.J. 91199 The Chemistry of Antistatic Additives Anderson, J.W. 87036 Contaminated Antistatic Polyethylene Anderson, R.E. 2001238 Human Body Model, Machine Model, and Charged Device Model ESD Testing of Surface Micromachined Microelectromechanical Systems (MEMS) Anderson, W.E. 81075 Selection of Packaging Materials for Electrostatic Discharge-Sensitive (ESDS) Items 83087 Permanence of the Antistatic Property of Commercial Antistatic Bags and Tote Boxes 84007 Hazards of Static Charges and Fields at the Work Station 85111 Perforated Foil Bags: Partial Transparency and Excellent ESD Protection 87041 Electrostatic Discharge (ESD) Control in an Automated Process 89023 Controlling Voltage on Personnel Anderson, W.R. 98054 ESD Protection for Mixed Voltage I/O Using NMOS Transistors Stacked in a Cascode Configuration 98086 Cross Reference ESD Protection for Power Supplies 99088 ESD Protection under Wire Bonding Pads 99212 A Strategy for Characterization and Evaluation of ESD Robustness of CMOS Semiconductor Technologies 2003059 ESD Protection Design Challenges for a High Pin-Count Alpha Microprocessor in a 0.13µm CMOS SOI Technology 2009101 Metal and Silicon Burnout Failures from CDM ESD Testing 2010203 Investigation on Output Driver with Stacked Devices for ESD Design Window Engineering Ando, K. 92076 An Advanced ESD Test Method for Charged Device Model
Andreini, A. 2001102 Experimental Analysis and Electro-Thermal Simulation of Low- and High-Voltage ESD Protection Bipolar Devices in a Silicon-on-Insulator Bipolar-CMOS-DMOS Technology 2003088 Characterization and Modeling of Transient Device Behavior Under CDM ESD Stress 2003319 Test Circuits for Fast and Reliable Assessment of CDM Robustness of I/O Stages 2003328 A Traceable Method for the Arc-free Characterization and Modeling of CDM-Testers and Pulse Metrology Chains 2004107 Study of CDM Specific Effects for a Smart Power Input Protection Structure 2006032 Novel Technique to Reduce Latch-up Risk Due to ESD Protection Devices in Smart Power Technologies 2006274 Analysis of the Triggering Behavior of Low Voltage BCD Single and Multi-Finger gc-NMOS ESD Protection Devices 2007058 CDM Circuit Simulation of a HV Operational Amplifier Realized in 0.35µm Smart Power Technology 2008211 Novel 190V LIGBT-Based ESD Protection for 0.35µm Smart Power Technology Realized on SOI Substrate 2013105 Power-to-Failure Investigation for PNP-based ESD Protections: From ns to ms 2013164 HBM ESD EDA Check Method Applied to Complete Smart Power IC’s – Functional Initialization and Implementation 20153A2 Schematic-Level and Layout-Level ESD EDA Check Methodology Applied to Smart Power IC’s – Initialization and Implementation 20162A1 HV ESD Diodes Investigation under vf-TLP Stresses: TCAD Approach 20173B2 EDA Checker for Identification of Excessive ESD Voltage Drop – Implementation to Smart Power ICs 20187A3 CDM Stress Rise Time: Impact on Forward Recov-ery Effect for HV ESD Protections 20201B1 Impact of Alternative CDM Methods on HV ESD Protections Behavior 20202B2 Transmission Line Pulse (TLP) Statistical Characterization Approach Andresen, B. 92234 A Successful HBM ESD Protection Circuit for Micron and Sub-Micron Level CMOS Andrieu, F. 2010185 Improved ESD Protection in Advanced FDSOI by using Hybrid SOI/Bulk Co-Integration Angeli, S. 20173B2 EDA Checker for Identification of Excessive ESD Voltage Drop – Implementation to Smart Power IC’s Angelopoulos, M. 94226 Electrically Conducting Polyanilines for Electrostatic Dissipation 95225 Cross-Linkable Conducting Polymer Coatings Angyal, M. 20155A2 3D Integration ESD Protection Design and Analysis Ansari, S. 2002382 Copper Interconnect Microanalysis and Electromigration Reliability Performance due to the Impact of TLP ESD Antinone, R.J. 80184 Microcircuit Electrical Overstress Tolerance Testing and Qualification Antonevich, J.N. 83076 Measuring Effectiveness of Air Ionizers Aoki, O. 2006152 Radiated ESD Noise of 5GHz-band from Walkers Appaswamy, A. 20165A2 Impact of Sub-Threshold SOA on ESD Protection Schemes Araki, K. 20168A1 Mirrored Power Distribution Network Noise Injection for Soft Failure Root Cause Analysis
Arbess, H. 2011045 High Temperature Operation MOS-IGBT Power Clamp for Improved ESD Protection in Smart Power SOI Technology 2013258 Transient-TLP (T-TLP): A Simple Method for Accurate ESD Protection Transient Behavior Measurement Argard, P.V. 87164 A New TTL-CMOS Input Buffer and an Inverter with Process Independent Threshold Voltage Arifin, S. 2009055 Space Charge Balance Sensing for Static Control Arimura, M. 2008174 Electrostatic Control System Using Ceramic Transformer Armendariz, M.G. 80104 Surprising Patterns of CMOS Susceptibility to ESD and Implications on Long-Term Reliability Armer, J. 2001001 Multi-Finger Turn-on Circuits and Design Techniques for Enhanced ESD Performance and Width-Scaling 2001022 GGSCRs: GGNMOS Triggered Silicon Controlled Rectifiers for ESD Protection in Deep Sub-Micron CMOS Processes 2002010 High Holding Current SCRs (HHI-SCR) for ESD Protection and Latch-up Immune IC Operation 2003250 Active-Area-Segmentation (AAS) Technique for Compact, ESD Robust, Fully Silicided NMOS Design Arnould, J.D. 2010021 A Novel Physical Model for the SCR ESD Protection Device 2011179 Scalable Modeling Studies on the SCR ESD Protection Device 20206A2 Study of Inter-Power Domain Failures During a CDM Event 20224A1 Analysis of Input Receiver Transistors Behavior During a CDM Event Asadi, R. 20241A3 A Physics-Based Model for ESD Protection Devices with Open Base BJT Configuration Asam, M. 20173B4 Influence of Self-Heating on ESD Current Distribution in Metal Lines Ash, M.S. 81242 Non-Linear Kinetics of Semiconductor Junction Thermal Failure 83122 Semiconductor Junction Non-Linear Failure Power Thresholds: Wunsch-Bell Revisited Ashby, P. 90119 Standard ESD Testing of Integrated Circuits Asheghi, M. 2004356 Comparison of Thermal Response of GMR Sensor Subjected to HBM and CDM Transients Ashton, R.A. 99212 A Strategy for Characterization and Evaluation of ESD Robustness of CMOS Semiconductor Technologies 2001435 Characterization of a 0.16µm CMOS Technology using SEMATECH ESD Benchmarking Structures 2003372 Standardization of the Transmission Line Pulse (TLP) Methodology for Electrostatic Discharge (ESD) 2004153 Voltages Before and After HBM Stress and Their Effect on Dynamically Triggered Power Supply Clamps 2005141 Voltages Before and After Current in HBM Testers and Real HBM 2006325 Pre Pulse Voltage in the Human Body Model 2006353 HBM Tester Parasitic Effects on High Pin Count Devices with Multiple Power and Ground Pins 2008021 Characterization of Off Chip ESD Protection Devices 2008040 VF-TLP Round Robin Study, Analysis and Results 2009188 FCDM Measurements of Small Devices 2012032 Progress towards a Joint ESDA/JEDEC CDM Standard: Methods, Experiments, and Results 2012060 HMM Round Robin Study: What to Expect When Testing Components to the IEC 61000-4-2 Waveform 2013268 Activities Towards a New Transient Latch-up Standard
20163B3 HMM Single Site Testing: Can We Reproduce Component Failure Level with the HMM Document? 20164A2 JS-002 Module and Product CDM Result Comparison to JEDEC and ESDA CDM Methods 20194A4 HMM Failure Level Variations Revisited 20222B1 Hidden Threats During Automated Latch-up Testing Aslett, R. 93239 Designing On-Chip Power Supply Coupling Diodes for ESD Protection and Noise Immunity 94141 Core Clamps for Low Voltage Technologies Assaderaghi, F. 96291 CMOS-ON-SOI ESD Protection Networks 97210 Dynamic Threshold Body- and Gate-Coupled SOI ESD Protection Networks 99105 Electrostatic Discharge (ESD) Protection in Silicon-on-Insulator (SOI) CMOS Technology with Aluminum and Copper Interconnects in Advanced Microprocessor Semiconductor Chips 2000029 Silicon-On-Insulator Dynamic Threshold ESD Networks and Active Clamp Circuitry Atwood, B.C. 2007273 Effect of Large Device Capacitance on FICDM Peak Current Austin, P. 20152A1 An Electrostatic-Discharge-Protection Solution for Silicon-Carbide MESFET Autizi, E. 2008272 EOS/ESD Sensitivity of Functional RF-MEMS Switches Averill, J.A. 86188 Design and Test Results for a Robust CMOS VLSI Input Protection Network Avery, L.R. 83177 Using SCRs as Transient Protection Structures in Integrated Circuits 85001 IC Technology: Where it is Going and What it Means for the ESD Industry 86156 Study of Antistatically Coated Shipping Tubes Using Static Decay and Triboelectric Tests 87088 Charged Device Model Testing; Trying to Duplicate Reality 87186 ESD Protection Structures to Survive the Charged Device Model (CDM) [BPR] 91120 Beyond MIL HBM Testing: How To Evaluate the Real Capability of Protection Structures 98301 Investigation into Socketed CDM (SDM) Tester Parasitics 2001001 Multi-Finger Turn-on Circuits and Design Techniques for Enhanced ESD Performance and Width-Scaling 2001022 GGSCRs: GGNMOS Triggered Silicon Controlled Rectifiers for ESD Protection in Deep Sub-Micron CMOS Processes Avlyanov, J. 99268 Processable ESD Control Materials Filled With Tunable Intrinsically Conductive Polymer Nanocomposites Axelrad, V. 2005100 Chip Level Layout and Bias Considerations for Preventing Neighboring I/O Cell Interaction-Induced Latch-up and Inter-Power Supply Latch-up in Advanced CMOS Technologies Axelrod, V. 2008030 HBM ESD Failures Caused by a Parasitic Pre-Discharge Current Spike Ayling, A. 20204A1 Balancing the Tradeoff Between Performance and Mis-Trigger Immunity in Active Feedback Based High Voltage Tolerant Power Clamps Azaïs, F. 2003233 STMSCR: A New Multi-Finger SCR-Based Protection Structure Against ESD 2005053 Physics and Design Optimization of ESD Diode for 0.13 µm PD-SOI Technology 2006166 Partially Depleted SOI Body-Contacted MOSFET- Triggered Silicon Controlled Rectifier for ESD Protection 2007165 Characterization of the Transient Behavior of Gated/STI Diodes and their Associated BJT in the CDM Time Domain 2008067 A Physics-Based Compact Model for ESD Protection Diodes Under Very Fast Transients
Aminuddin, M. A. 20222C2 Tracing & Debugging of ESD Failures in a Module Assembly Line Baba, S. 2004125 ESD Protection Design Using a Mixed-Mode Simulation for Advanced Devices Bach, E. 20182B3 ESD System Level Simulation of MEMS Sensor Modules Backers, I. 2010167 On-Chip ESD Protection with Improved High Holding Current SCR (HHISCR) Achieving IEC 8 kV Contact System Level 20175B3 Low Capacitive Dual Bipolar ESD Protection Bade, L. 2008076 Discrete ESD Protection Diode During a System Level Pulse: Comparison of Simulation With Measurements Badenes, G. 97308 Influence of Well Profile and Gate Length on the ESD Performance of a Fully Silicided 0.25 um CMOS Technology Bae, B. 20191B3 A Low-Voltage Microwave Plasma Ionizer Without the ESD Risk Due to a High Voltage Source 20213A3 Proposed ESD Models of Dust Cleaners and Analysis of ESD Failures in Automotive Headlamps 2021M22 A Low-Voltage Microwave Plasma Ionizer Without Reduced Ionizing Performance Due to Particle Fuzzballs Baelde, W. 90119 Standard ESD Testing of Integrated Circuits Bafleur, M. 2002281 Design Guidelines to Achieve a Very High ESD Robustness in a Self-Biased NPN 2002348 Investigations for a Smart Power and Self-Protected Device Under ESD Stress Through Geometry and Design Considerations for Automotive Applications 2004174 ESD Induced Latent Defects in CMOS ICs and Reliability Impact 2006069 Area-Efficient Reduced and No-Snapback PNP-based ESD Protection in Advanced Smart Power Technology 2007304 Characterization and Modeling Methodology for IC’s ESD Susceptibility at System Level Using VF-TLP Tester 2009165 Accurate Transient Behavior Measurement of High-Voltage ESD Protections Based on a Very Fast Transmission-Line Pulse System 2009314 Local ESD Protection Structure Based on Silicon Controlled Rectifier Achieving Very Low Overshoot Voltage 2010011 TCAD Study of the Impact of Trigger Element and Topology on Silicon Controlled Rectifier Turn-on Behavior 2011045 High Temperature Operation MOS-IGBT Power Clamp for Improved ESD Protection in Smart Power SOI Technology 2011241 Investigation of Statistical Tools to Analyze Repetitive HMM Stress Endurance of System-Level ESD Protection 2011329 ESD System Level Characterization and Modeling Methods Applied to a LIN Transceiver 2011343 Investigating the Probability of Susceptibility Failure Within ESD System Level Consideration 2013258 Transient-TLP (T-TLP): A Simple Method for Accurate ESD Protection Transient Behavior Measurement 2014053 Novel 3D Back--to--Back Diodes ESD Protection 20154B1 TLP-Based Human Metal Model Stress Generator and Analysis Method of ESD Generators 20167A3 From Quasi-Static to Transient System Level ESD Simulation: Extraction of Turn-on Elements Baghini, M.S. 2009221 IGBT Plugged in SCR Device for ESD Protection in Advanced CMOS Technology Baglee, D.A. 85045 ESD Design Considerations for ULSI Bai, W. 2011323 Machine Model Evaluation and Interconnect Effect Study for TMR HGA
Bailey, R. 98328 Current Transients and the Guzik: A Case Study and Methodology for Qualifying a Spin Stand for GMR Testing Baird, M. 2000465 Verify ESD: A Tool for Efficient Circuit Level ESD Simulations of Mixed-Signal ICs 2010151 Correlation between System Level and TLP Tests Applied to Stand-Alone ESD Protections and Commercial Products Baker, L. 89175 A "Waffle" Layout Technique Strengthens the ESD Hardness of the NMOS Output Transistor Baker, R.P. 80104 Surprising Patterns of CMOS Susceptibility to ESD and Implications on Long-Term Reliability Bakulin, A. 2002062 Optimization of Input Protection Diode for High Speed Applications Bala, W. 2003080 Transient Latch-up: Experimental Analysis and Device Simulation 2004299 Development Strategy for TLU-Robust Products Balevsky, A. 2014359 Over-Voltage Protection Strategies for LED Based Light Source Systems and Other Applications Baliga, B.J. 93001 Smart Power Technology: An Elephantine Opportunity Ball, A. 96241 Antistatic Masking Tapes for Solder Flux Reflow Processing of Printed Circuit Boards Ballarin, G. 20153A2 Schematic-Level and Layout-Level ESD EDA Check Methodology Applied to Smart Power IC’s – Initialization and Implementation 20158A3 Practical HBM Testing with Statistical Pin Combinations Balmain, K.G. 95066 Spacecraft and Human Electrostatic Discharge: A Comparison of the Two Phenomena 95090 Human Hand/Metal ESD and Its Physical Simulation Ban, T. 2011197 Capturing Real World ESD Stress with Event Detector Ban, Y. 20211B4 HBM and CDM ESD Performance of Advanced Silicon Photonic Components 20243A1 ESD Robustness of Germanium Photodetectors in Advanced Silicon Photonics Technology Bandy, W. 2012120 ESD Protection of MR Sensors Using a Dissipative Shunt Banerjee, K. 2001191 Invited Paper: Interconnect Reliability Under ESD Conditions: Physics, Models, and Design Guidelines 2001355 Analysis and Optimization of Distributed ESD Protection Circuits for High-Speed Mixed-Signal and RF Applications 2009001 Prospects of Carbon Nanomaterials in VLSI for Interconnections and Energy Storage 2012304 ESD Characterization of Atomically-Thin Graphene Banghart, E. 20171A3 Enhanced nFinFET ESD Performance Bansal, N. 20193A1 3.3V ESD Clamp Structure Susceptibility Towards Pseudo LU in 22FDSOI
Bao, Z. 2021M21 New Advanced Materials for ESD Mats Barbato, M. 2010433 A Comprehensive Study of MEMS Behavior under EOS/ESD Events: Breakdown Characterization, Dielectric Charging, and Realistic Cures Bardy, S. 2001110 Human Body Model Test of a Low Voltage Threshold SCR Device: Simulation and Comparison with the Transmission Line Pulse Test Bargstädt-Franke, S. 2003080 Transient Latch-up: Experimental Analysis and Device Simulation 2004067 From the ESD Robustness of Products to the System ESD Robustness 2004299 Development Strategy for TLU-Robust Products Baril, L. 2002306 Standardized Direct Charge Device Model ESD Test For Magnetoresistive Recording Heads I 2002315 Standardized Direct Charge Device Model ESD Test For Magnetoresistive Recording Heads II 2003419 Effect of ESD Transients on Noise in GMR Recording Heads 2004001 Electromagnetic Field Induced Degradation of Magnetic Recording Heads in a GTEM Cell 2004352 Effects of ESD Transients on Noise in Tunneling Recording Heads Barker, P. 2012414 Characterizing Devices Using the IEC 6100-4-5 Surge Stress Barnett, H. 99043 A Study of ESD Induced Lockups in a Semiconductor Photolithography Area Barnum, J.R. 81229 Electrical Overstress Damage in Silicon Solar Cells 91026 Sandia's Severe Human-Body Electrostatic Discharge Tester (SSET) Barrett, R. 2004141 Formation and Suppression of a Newly Discovered Secondary EOS Event in HBM Test Systems Barth, J. 96167 Charged Device Model (CDM) Metrology: Limitations and Problems 96211 Measurements of ESD HBM Events, Simulator Radiation, and Other Characteristics Toward Creating a More Repeatable Simulation or; Simulators Should Simulate 98029 Metrology and Methodology of System Level ESD Testing 98290 Characterization and Optimization of a Bipolar ESD –Device by Measurements and Simulations 98301 Investigation into Socketed CDM (SDM) Tester Parasitics 99178 Developing a Transient Induced Latch-up Standard for Testing Integrated Circuits 99203 Issues Concerning CDM ESD Verification Modules-The Need to Move to Alumina 2000072 The Importance of Standardizing CDM ESD Test Head Parameters to Obtain Data Correlation 2000085 TLP Calibration, Correlation, Standards, and New Techniques 2001453 Correlation Considerations: Real HBM to TLP and HBM Testers 2002155 Correlation Considerations II: Real HBM to HBM testers 2003179 Real HBM & MM - The dV/dt Threat 2003372 Standardization of the Transmission Line Pulse (TLP) Methodology for Electrostatic Discharge (ESD) 2005141 Voltages Before and After Current in HBM Testers and Real HBM 2006353 HBM Tester Parasitic Effects on High Pin Count Devices with Multiple Power and Ground Pins 2008040 VF-TLP Round Robin Study, Analysis, and Results 2009286 Using VFTLP Data to Design for CDM Robustness 2012032 Progress towards a Joint ESDA/JEDEC CDM Standard: Methods, Experiments, and Results 2012060 HMM Round Robin Study: What to Expect When Testing Components to the IEC 61000-4-2 Waveform 2013140 On-Chip System Level ESD Protection for Class G Audio Power Amplifiers
20163B3 HMM Single Site Testing: Can We Reproduce Component Failure Level with the HMM Document? 20164A1 Improving CDM Measurements with Frequency Domain Specifications Baruah, A. 79126 An Electrothermal Model for Current Filamentation in Second Breakdown of-Silicon-on Sapphire Diodes Batchelder, J.S. 91038 Technique for Generating Contamination-Free Ionized Air Using Focused Laser Light Batra, J. 20171B3 An ESD Case Study with High Speed Interface in Electronics Manufacturing and its Future Challenge Batra, V. 20159A2 EOS Characterization Methodology Applied to Disable Feature of ESD Power Clamps Bauduin, B. 94301 A Comparative Study of "Low Cost" 1.3 µm Laser Diodes: ESD Performance Baum, K. 91151 Detection of ESD-Induced Non Catastrophic Damage in P-Channel Power MOSFETs Baumann, C. 2010049 Triggering of Transient Latch-up (TLU) by System Level ESD Baumgartner, G. 84025 Electrostatic Measurement for Process Control 84097 Testing of Electrostatic Materials Fed. Std. 101C, Method 4046.1 85124 ESD Analysis of Masking Tape Operations 87018 A Method to Improve Measurements of ESD Dissipative Materials 90097 Electrostatic Discharge Protective Bag Test - Analysis of EIA Standard 541 92009 The Misconceptions of Air Flow as a Tribocharging Source 95262 Electrostatic Decay Measurement Theory and Applications 96156 ESD Demonstrations to Increase Engineering & Manufacturing Awareness 97068 Analysis of ESD Glove Use 98224 EOS Analysis of Soldering Iron Tip Voltage 2001281 A Study of the Electrical Properties of Polymeric Materials Used for Gloves and Finger Cots Bayer, M.J. 2003017 Boosted and Distributed Rail Clamp Networks for ESD Protection in Advanced CMOS Technologies Baynes, C.C. 90151 Failure Analysis of Electrostatic Sensitive ECL Gate Arrays Bazarian, A. 80044 Gas Tube Surge Arresters for Control of Transient Voltages Beall, J. R. 83198 A Study of ESD Latent Defects in Semiconductors Beamer, B. 91210 A New Permanent ESD and Corrosion Resistant Material [BPR] Beaudoin, F. 2004174 ESD Induced Latent Defects in CMOS ICs and Reliability Impact Beckrich-Ros, H. 2008067 A Physics-Based Compact Model for ESD Protection Diodes Under Very Fast Transients 2008088 A Scalable Compact Model of Interconnects Self-Heating in CMOS Technology 2010021 A Novel Physical Model for the SCR ESD Protection Device 2011179 Scalable Modeling Studies on the SCR ESD Protection Device 2012015 ESD Design Challenges in 28 nm Hybrid FDSOI/Bulk Advanced CMOS Process
Beebe, S.G. 96265 Methodology for Layout Design and Optimization of ESD Protection Transistors 98259 Simulation of Complete CMOS I/O Circuit Response to CDM Stress 2004248 ESD Protection for SOI Technology Using an Under-The-Box (Substrate) Diode Structure 2005421 SOI Lateral Diode Optimization for ESD Protection in 130nm and 90nm Technologies 2007185 Double Well Field Effect Diode: Lateral SCR-like Device for ESD Protection of I/Os in deep Sub-Micron SOI 2008235 ESD Device Design Strategy for High Speed I/O in 45nm SOI Technology 2009101 Metal and Silicon Burnout Failures from CDM ESD Testing 2010203 Investigation on Output Driver with Stacked Devices for ESD Design Window Engineering Beetner, D.G. 20178A1 On-Chip Sensors to Measure Level of Transient Events 20206A3 Race Conditions Among Protection Devices for a High Speed I/O Interface 20212B2 Ω Disk Resistor Full-Wave Modeling for JS-002 Standard 20221A2 Determining the Peak Voltage During TVS Switching at the I/O of an IC Using Component Measurement Data 20235A1 A Combined Model for Transient and Self-Heating of Snapback Type ESD Protection Devices 20241A3 A Physics-Based Model for ESD Protection Devices with Open Base BJT Configuration Bèges, R. 20154B1 TLP-Based Human Metal Model Stress Generator and Analysis Method of ESD Generators Belisle, D. 2002163 A New ESD Model: The Charged Strip Model Bell, D.A. 2010097 Hierarchical Verification of Chip-Level ESD Design Rules Bellens, R. 97240 Study of the ESD Behaviour of Different Clamp Configurations in a 0.35 µm CMOS Technology Bellew, P. 2000041 Optimizing the Performance of a Composite ESD Circuit Protection Device 2000111 TLP Measurements for Verification of ESD Protection Device Response Bellmore, D. 2001141 Anodized Aluminum Alloys, Insulator or Not? 2002223 Controlling ESD in Automated Handling Equipment 2004200 CPM Study: Discharge Time and Offset Voltage, Their Relationship to Plate Geometry 2004219 Characterizing Automated Handling Equipment Using Discharge Current Measurements 2005195 Characterizing Automated Handling Equipment Using Discharge Current Measurements II 2006240 Trends in External Ionizer Monitoring and Control 20194B4 Determining the Proper Methods of Measuring a Conveyor Belt’s Resistance to Ground Beloni, E. 2010325 ESD Stimulated Ignition of Metal Powders Beltman, R.A.M. 90157 Simulation of Thermal Runaway During ESD Events 91098 Physics of Electro-Thermal Effects in ESD Protection Devices Bendix, P. 2000456 Chip-Level Simulation for CDM Failures in Multi-Power ICs 2005100 Chip Level Layout and Bias Considerations for Preventing Neighboring I/O Cell Interaction-Induced Latch-up and Inter-Power Supply Latch-up in Advanced CMOS Technologies Bennett, D. 2003372 Standardization of the Transmission Line Pulse (TLP) Methodology for Electrostatic Discharge (ESD) 2004141 Formation and Suppression of a Newly Discovered Secondary EOS Event in HBM Test Systems
Benoist, T. 2010185 Improved ESD Protection in Advanced FDSOI by using Hybrid SOI/Bulk Co-Integration 2012015 ESD Design Challenges in 28 nm Hybrid FDSOI/Bulk Advanced CMOS Process Berbeco, G.R. 80001 Passive Static Protection: Theory and Practice 82124 Characterization of ESD Safe Requirements for Floor Surfaces Berkowitz, M.B. 89032 Modular ESD Certification Training Program 90027 ESD Controls in Hazardous High Voltage Environments Berndt, H. 2001267 A Study of the Variables of Electrodes Used in the Measurement of Table and Floor Materials and How They Affect the Test Results Bernett, M.K. 82115 Electroactive Polymers as Alternate ESD Protective Materials Bernhard Stein, B. 20231A3 Novel ESD Characterization Method for Bipolar Devices Using a Combined TLP System with Dynamic Base Bias Bernier, J.C. 94214 CDM Events in Automated Test Handlers and Environmental Testing - A Case History 95110 ESD Improvements for Familiar Automated Handlers 96117 Die Level CDM Testing Duplicates Assembly Operation Failures 97083 ESD Sources Pinpointed by Analysis of Radio Wave Emissions 99168 Test Methodologies for Detecting ESD Events in Automated Processing Equipment 2000097 A Method for Determining a Transmission Line Pulse Shape that Produces Equivalent Results to Human Body Model Testing Methods 2003372 Standardization of the Transmission Line Pulse (TLP) Methodology for Electrostatic Discharge (ESD) 2005195 Characterizing Automated Handling Equipment Using Discharge Current Measurements II Berning, D.W. 79116 Reverse-Bias Second Breakdown in Power Transistors Berthet, F. 2014393 Electrical Overstress Robustness and Test Method for ICs Bertonnaud, S. 2012388 IEC System Level ESD Challenges and Effective Protection Strategy for USB2 Interface Bertrand, G. 2002281 Design Guidelines to Achieve a Very High ESD Robustness in a Self-Biased NPN Besse, P. 2002348 Investigations for a Smart Power and Self-Protected Device Under ESD Stress Through Geometry and Design Considerations for Automotive Applications 2006069 Area-Efficient Reduced and No-Snapback PNP-based ESD Protection in Advanced Smart Power Technology 2010151 Correlation between System Level and TLP Tests Applied to Stand-Alone ESD Protections and Commercial Products 2011329 ESD System Level Characterization and Modeling Methods Applied to a LIN Transceiver 2012409 Impact of Snapback Behavior on System Level ESD Performance with Single and Double Stack of Bipolar ESD Structures 20154B1 TLP-Based Human Metal Model Stress Generator and Analysis Method of ESD Generators 20175B2 High-Performance Bi-Directional SCR Developed on a 0.13 um SOI-Based Smart Power Technology for Automotive Applications
Beyne, E. 20155A1 ESD Protection Design in Active-Lite Interposer for 2.5 and 3D Systems-in-Package 2023M12 ESD Mitigation for 3D IC Hybrid Bonding 2023M23 ESD Process Assessment of 2.5D and 3D Bonding Technologies Bhar, T.N. 79027 Proposed MIL-STD and MIL-HDBK for an Electrostatic Discharge Control Program -- Background and Status -- Bhat, N. 20172A2 On the ESD Behavior of AlGaN/GaN Schottky Diodes and Trap Assisted Failure Mechanism Bhatia, K. 2007019 Layout Guidelines for Optimized ESD Protection Diodes 2007080 A Kelvin Transmission Line Pulsing System with Optimized Oscilloscope Ranging Bhattacharya, M. 20232A2 Interplay of Surface Passivation and Electric Field in Determining ESD Behavior of p-GaN Gated AlGaN/GaN HEMTs Bhooshan, R. 20156A2 A New Full-Chip Verification Methodology to Prevent CDM Oxide Failures Biegel, M.G. 94085 Charged Device Damage of PLCCs Inside an Antistatic Shipping Tube - A Case History Biermann, G. 93143 A Statistical Method for the Detection of Gate Oxide Breakdowns Due To Fast EOS Events, Such As ESD, On Power DIMOS Devices 97170 Grounding Personnel via the Floor/Footwear System Bigaouette, R.J. 90169 Degraded Device Detection Billy, S. 20153A3 A Comprehensive ESD Verification Flow at Transistor Level for Large SoC Designs Bilodeau, T.M. 88147 A Novel High Fidelity Technique to View In-Situ ESD Stress Voltage Waveforms 89043 Theoretical and Empirical Analyses of the Effects of Circuit Parasitics on the Calibration of HBM ESD 90131 The Electrostatic Discharge Sensitivity of GaAs MMIC Amplifiers Bin, L. 98135 Discussion on Electric Parameters of Standard for Anti-Electrostatic Floor Bin, T-Y. 20212A2 NBL Causing Low Latch-up Immunity Between HV-PMOS and LV-P/NMOS in a 0.15-μm BCD Process Bingold, B. 91144 Package Effects on Human Body and Charged Device ESD Tests Birk, M. 97027 Novel Concept for High Level Overdrive Tolerance of GaAs Based FETs Black, E.P. 91015 Real Circuit Performance of ESD Protection Devices Blackburn, D.L. 79116 Reverse-Bias Second Breakdown in Power Transistors Blanc, D. 2013105 Power-to-Failure Investigation for PNP-based ESD Protections: From ns to ms
Blanc, F. 2001110 Human Body Model Test of a Low Voltage Threshold SCR Device: Simulation and Comparison with the Transmission Line Pulse Test 2006077 ESD Protection for the High-Voltage CMOS Technologies 2007047 Designing HV Active Clamps for HBM Robustness 2008099 A Methodology for the ESD Test Reduction for Complex Devices Blankenagel, J. 89050 A High Voltage Pulse Generator for ESD Simulation Blankstein, S. 98124 Outgassing, Volatile Organic Content, and Contamination Content of Materials Used in Today’s Electronics Workplace Blinde, D.R. 81009 Quantitative Effects of Relative & Absolute Humidity on ESD Generation/Suppression 83067 The Room Air Ionization System, a Better Alternative than 40% Relative Humidity [BPR] Blitshteyn, M. 83076 Measuring Effectiveness of Air Ionizers Blore, R.A. 79041 Reliability of EOS Screened Gold Doped 4002 CMOS Devices Bobde, M. 2008083 Potential Barrier Based Clamp: A New Device Structure for Low Voltage Triggering Bock, K.H. 90193 Improved ESD-Protection of GaAs-FET Microwave Devices by New Metallization Strategy 92168 Fieldemitter-Based ESD-Protection Circuits for High Frequency Devices and IC's [BPP] 96302 A Compact Model for the Grounded-Gate NMOS Behaviour Under CDM ESD Stress 97001 ESD Issues in Compound Semiconductor High-Frequency Devices and Circuits 97308 Influence of Well Profile and Gate Length on the ESD Performance of a Fully Silicided 0.25 um CMOS Technology 98177 Non-Uniform Triggering of gg-nMOSt Investigated by Combined Emission Microscopy and Transmission Line Testing 98290 Characterization and Optimization of a Bipolar ESD –Device by Measurements and Simulations 98301 Investigation into Socketed CDM (SDM) Tester Parasitics 99095 Influence of gate length on ESD-performance for deep sub micron CMOS technology 2009135 Capacitive Coupled TLP (CC-TLP) and the Correlation with the CDM Boday, D 2012120 ESD Protection of MR Sensors Using a Dissipative Shunt Boehm, A. 20245A1 TDDB of Sensitive High-K Gate Dielectrics – Revisited for CDM Boehm, D. 98233 Magneto Optical Static Event Detector 99168 Test Methodologies for Detecting ESD Events in Automated Processing Equipment 2000193 Advances in Magneto Optical Static Event Detector Technology Bogani, A. 2013164 HBM ESD EDA Check Method Applied to Complete Smart Power IC’s – Functional Initialization and Implementation 20153A2 Schematic-Level and Layout-Level ESD EDA Check Methodology Applied to Smart Power IC’s – Initialization and Implementation 20173B2 EDA Checker for Identification of Excessive ESD Voltage Drop – Implementation to Smart Power IC’s
Bolasny, R.E. 80213 Static Control Systems Bonfert, D. 99178 Developing a Transient Induced Latch-up Standard for Testing Integrated Circuits Bönisch, S. 2001373 Broadband Measurement of ESD Risetimes to Distinguish between Different Discharge Mechanisms Bontekoe, F. 90119 Standard ESD Testing of Integrated Circuits Bookin, W. 2007138 ESD Damage and Solutions in Tape Head Manufacturing Boone, W. 98010 Evaluation of Cleanroom/ESD Garment Fabrics: Test Methods and Results 98328 Current Transients and the Guzik: A Case Study and Methodology for Qualifying a Spin Stand for GMR Testing 99361 Using HGA Antennas to Measure EMI; Establishing and Correlating Damage Thresholds of GMR Heads 99373 A Study of Head Stack Assembly Sensitivity to ESD 2002326 Impact of Insulating “Conductive” Materials on Disk Drive ESD Robustness 2004008 Wire Bonding Tip Study for Extremely ESD Sensitive Devices Bordeos, R. 2000184 A Case Study on Hidden ESD Events of GMR HGA Dynamic Test Fixture 2000485 Investigation of GMR sensor microstructural changes induced by HBM ESD using advanced Microscopy Approach 2001175 A Study of GMR Read Sensor Induced by Soft ESD Using Magnetoresistive Sensitivity Mapping (MSM) 2002147 Magnetoresistive Sensitivity Mapping (MSM) and Dynamic Electrical Test (DET) Correlation Study on GMR Sensor Induced by Low Threshold ESD Stress 2002321 The Practical Approach of ESD Control Solution in Headstack Assembly (HSA) Manufacturing Bordoloi, B.K. 88113 Characterization of Corrosivity of Antistatic Packaging Materials Borgmans, C. 93177 Selecting Materials for Protection Against ESD Using an ESD Shielding Effectiveness Meter Borjesson, A. 95253 A Method for Measurement of Triboelectric Charging Borlongan, M.A. 2007222 Preventing Arcing Damage on Radio Frequency Device Wafer by Controlling ESD Resistively Level of Water for Saw and Wash Boroni, A. 20158A3 Practical HBM Testing with Statistical Pin Combinations 20187A3 CDM Stress Rise Time: Impact on Forward Recov-ery Effect for HV ESD Protections 20201B1 Impact of Alternative CDM Methods on HV ESD Protections Behavior 20202B2 Transmission Line Pulse (TLP) Statistical Characterization Approach Borremans, J. 2007242 T-Diodes-A Novel Plug-and-Play Wideband RF Circuit ESD Protection Methodology 2009352 A 4.5 kV HBM, 300 V CDM, 1.2 kV HMM ESD Protected DC-to-16.1 GHz Wideband LNA in 90 nm CMOS Bos, P. 90119 Standard ESD Testing of Integrated Circuits Bosch, W. 2013191 Powered System-Level Conductive TLP Probing Method for ESD/EMI Hard Fail and Soft Fail Threshold Evaluation
Boschke, R. 20151A3 VFTLP Characteristics of ESD Protection Diodes in Advanced Bulk FinFET Technology 20151A4 ESD Characterization of Diodes and ggMOS in Germanium FinFET Technologies 20161A1 ESD Protection Design in a-IGZO TFT Technologies 20166A2 VFTLP Characteristics of ESD Devices in Si Gate-All-Around (GAA) Nanowires 20176B1 VFTLP Characteristics of ESD Diodes in Bulk Si Gate-all-Around Vertically Stacked Horizontal Nanowire Technology Boselli, G. 99011 Investigations on Double-Diffused MOS (DMOS) transistors under ESD zap conditions 2001071 Modeling Substrate Diodes under Ultra High ESD Injection Conditions 2002257 Efficient pnp Characteristics of pMOS Transistors in Sub-0.13 um ESD Protection Circuits 2003008 A MOSFET Power Supply Clamp with Feedback Enhanced Triggering for ESD Protection in Advanced CMOS Technologies 2004132 Gate Oxide Failures Due to Anomalous Stress from HBM ESD Testers 2004146 The Effect of High Pin-Count ESD Tester Parasitics on Transiently Triggered ESD Clamps 2005043 Analysis of ESD Protection Components in 65nm CMOS Technology: Scaling Perspective and Impact on ESD Design 2005298 A Low Leakage Low Cost-PMOS Based Power Supply Clamp with Active Feedback for ESD Protection in 65nm CMOS Technologies 2010031 The Relevance of Long-Duration TLP Stress on System Level ESD Design 2010103 An Automated ESD Verification Tool for Analog Design 2010309 Solutions to Mitigate Parasitic NPN Bipolar Action in High Voltage Analog Technologies 2011069 Novel Technologies to Modulate the Holding Voltage in High Voltage ESD Protections 2012373 A Flexible Simulation Model for System Level ESD Stresses with Applications to ESD Design and Troubleshooting 2013133 Mutual Ballasting: A Novel Technique for Improved Inductive System Level IEC ESD Stress Performance for Automotive Applications 2013292 The Very Unusual Case of the IEC-Robust IC with Low HBM Performance 2013383 Predictive Modeling of Peak Discharge Current during Charged Device Model Test of Microelectronic Components 20157A1 Design and Optimization on ESD Self-Protection Schemes for 700V LDMOS in High Voltage Power IC 20163B2 Case Study of DPI Robustness of a MOS-SCR Structure for Automotive Applications 20176B3 A Novel, SCR-Based, Distributed Power Supply ESD Network for Advanced CMOS Technologies 20182B1 Study of Voltage Overshooting of Gate-Coupled Silicon Controlled Rectifier on HBM Protection 20208A1 Insights into the System Level IEC ESD Failure in High Voltage DeNMOS-SCR for Automotive Applications Bossard, P.R. 80017 ESD Damage from Triboelectrically Charged IC Pins 81057 Evaluation of Integrated Circuit Shipping Tubes [BPP] 83029 ESD by Static Induction 84040 A Room Ionization System for Electrostatic Charge and Dust Control 87214 Room Ionization: Can It Significantly Reduce Particle Contamination? Bossche, M.V. 2009158 The Application of Large-Signal Calibration Techniques Yields Unprecedented Insight During TLP and ESD Testing Botula, A. 2001326 Silicon Germanium Heterojunction Bipolar Transistor ESD Power Clamps and the Johnson Limit Bouangeune, D. 2012396 Current-Voltage, S-Parameter, LFN Properties in T-R-T Type ESD/EMI Filters with TVS Zener Diodes Developed Using Epitaxy-Based IPD Technology Bouchard, S. 92039 ESD - A Problem Beyond the Discrete Component Boujarra, W. 20153A3 A Comprehensive ESD Verification Flow at Transistor Level for Large SoC Designs
Bourgeat, J. 2009314 Local ESD Protection Structure Based on Silicon Controlled Rectifier Achieving Very Low Overshoot Voltage 2010011 TCAD Study of the Impact of Trigger Element and Topology on Silicon Controlled Rectifier Turn-on Behavior 2011082 ß Matriz Concept for ESD Power Devices, Demonstrators in C45 nm & C32 nm CMOS Technology 2013199 Point to Point ESD Protection Network, a Flexible and Competitive Strategy Demonstrated in Advanced CMOS 20152A2 Self-ESD-Protected Transmission Line Broadband in CMOS28nm UTBB-FDSOI 20172B3 ESD Protection Structure Enhancement Against Latch-up Issue Using TCAD Simulation 20197A1 Towards a TCAD Model for NMOS Drivers in 28FDSOI Under TLP & (vf)-TLP Transient Condition 20206A2 Study of Inter-Power Domain Failures During a CDM Event 20223A3 ESD Protection Based on Stacked SCRs With Adjustable Triggering Voltage for CMOS High-Voltage Application 20224A1 Analysis of Input Receiver Transistors Behavior During a CDM Event 20241B2 Can CC-TLP be Used as an Early Failure Analysis Tool? Bouyssou, E. 2011241 Investigation of Statistical Tools to Analyze Repetitive HMM Stress Endurance of System-Level ESD Protection Boverie, B. 88173 Coupling of ESD-Generated EMP to Electronics 89145 Simulation of the EMP From ESD Bowers, J.S. 83198 A Study of ESD Latent Defects in Semiconductors Boxleitner, W. 90054 ESD Stress on PCB Mounted ICs Caused by Charged Boards and Personnel 93139 Coaxial Probe to Measure ESD Voltage Waveforms with One Nanosecond Risetimes Bradford, J. 93201 ESD Packaging: An Environmental Perspective Bradza, E. 97170 Grounding Personnel via the Floor/Footwear System Branberg, G.A. 79055 Electro-Static Discharge and CMOS Logic Brandt, M.T. 90255 A Proposed Test Methodology for Evaluating the ESD Control Characteristics of Floor Materials Brankov, A. 2009396 Failure Detection with HMM Waveforms Braude, R. 93035 Setting Up an Effective Corporate ESD Program Bravaix, A. 2006284 Ultra-thin Gate Oxide Reliability in the ESD Time Domain 2007328 Reliability Aspects of Gate Oxide under ESD Pulse Stress Brederlow, R. 20243B3 System CDM Modeling for High-Speed Interface Devices Brennan, C.J. 2000239 Electrostatic Discharge Characterization of Epitaxial-Base Silicon-Germanium Heterojunction Bipolar Transistors 2004182 CDM Failure Modes in a 130nm ASIC Technology 2004166 ESD Design Automation for a 90nm ASIC Design System 2005126 Design Automation to Suppress Cable Discharge Event (CDE) Induced Latch-up in 90nm CMOS ASICs 2005380 Implementation of Diode and Bipolar Triggered SCRs for CDM Robust ESD Protection in 90nm CMOS ASICs Brennan, T.F. 83158 Invisible EOS/ESD Damage: How to Find it?
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