EOS/ESD Association Journal EOS/ESD Association, Inc. Inside this issue The Year’s Most Significant ESD Papers The EOS/ESD Association presents the year’s most significant ESD papers presented at the most important conferences that cover ESD. These papers are what we consider to be best-in-class. Introduction EOS/ESD Association, Inc. reviews and evaluates papers in the specific field of Electrostatic Discharge (ESD) that are presented at the world’s foremost conferences. This compilation comprises our selections. December 2024 Volume 3 All Papers are Reprinted with Permission © 2024 *EOS/ESD Association, Inc., **IEEE Introduction to Static Control for Roll-to-Roll Manufacturing** Voltage to Current Correlation for CDM Testing* Die-to-Die ESD Discharge Current Analysis* Distributed Protection for High-Speed Wireline Receivers* ESD Behavior of RF Switches and Importance of System Efficient ESD Design** ESD Challenges in 300nm Si Substrate of DTCO/STCO Scaling Options** ESD HBM 3kV Discharge for Monolithic GaN-on-Si HEMTs Integrated Chips** Poly-Bounded Silicon-Controlled-Rectifier for ESD Protection in FinFET Technology** ESD and Latch-up Design Verification Challenges in Packaged Parts and Modules** Design Optimization of Stacked-NMOS ESD Protection for MixedVoltage Application** Analysis of the Influence of Pin Position on CDM Peak Current Based on 2.5D and 2D Packaging** The Effect of the P-substrate Connection on the HBM Robustness of PType ESD Device** ESD Characteristics Improving of LVTSCR by Adding RC Triggering Circuit in 0.18 μm BCD Technology** Automotive Electronics EOS Failure Analysis and Diagnosis** Study of Efficient Design on Latchup in 130nm BCD Technology for High Voltage Application** The Influence of Gate-Series-Resistor on the ESD Protection and Switching Speed for 650V GaN-HEMT Circuit** Load-line Dependent Current Filament Dynamics in Nanoscale SCR Devices** Missing Trigger Circuit Action and Device Engineering for Conventional Nanoscale SCR** Reduced RC Time Constant High Voltage Tolerant Supply Clamp for ESD Protection in 16nm FinFET Technology** An Analysis of CDM-induced BTI-like Degradation using VF-TLP in Advanced FinFET Technology** On-Chip Single-Shot Pulse Generator for TDDB Characterization on a Sub-Nanosecond Timescale** Toward 0 V ESD Protection in 2.5D/3D Advanced Bonding Technology** MLESD: Machine Learning Assisted Faster On-Chip ESD Convergence Strategy** A Model for Corona Streamer Propagation on Glass during an Air Discharge** Metamaterial-Enabled Localization of Electrostatic Discharges using Time Reversal** Time-Dependent Resistance-Based Dynamic Behavior Model of Spark Gap Device under ESD Pulse** Modeling the ESD Dynamic Behavior of TVS Based on a Timedependent Resistance** Transmission Line Based CDM ESD Current Target to Overcome Bandwidth Limitations** Comparative analysis of calibration procedures in current and proposed editions of the IEC 61000-4-2 Standard**
2021 IEEE Industry Applications Society Annual Meeting (IAS)* Introduction to Static Control for Roll-to-Roll Manufacturing Abstract: Roll-to-Roll (R2R) manufacturing is used extensively in printing and flexible packaging industries. These markets exceed $ 30B annually in the US [1]. Static ignitions injury employees. Electrical charge stored on wound rolls shocks operators and disrupt machine operations. Static causes sheet sticking and sparks damage products. I estimate that injuries, product waste, and machine downtime caused by static electricity exceeds $600M annually (2%) in the US. This human suffering and waste may be eliminated by static control systems. Implementing effective static control on an R2R manufacturing line is a 4-step, data-driven process. First, identify sources of static charging with a static survey. Next, install static dissipaters forming a fault-tolerant static control system. Once static dissipaters are operational, verify that static is well controlled with another, static survey. Finally, maintain static performance by including static control in operations including regularly inspecting static dissipaters and including static control in Management of Change (MoC) procedures. Citation K. Robinson, "Introduction to Static Control for Roll-to-Roll Manufacturing," 2021 IEEE Industry Applications Society Annual Meeting (IAS), Vancouver, BC, Canada, 2021, pp. 1-6, doi: 10.1109/IAS48185.2021.9677304. Introduction to Static Control for Roll-to-Roll Manufacturing | IEEE Conference Publication | IEEE Xplore © 2021 IEEE. Reprinted, with permission, from 2021 IEEE Industry Applications Society Annual Meeting *Presentation featured at the 2024 EOS/ESD Symposium. 2023 EOS/ESD Symposium Voltage to Current Correlation for CDM Testing Abstract: CDM charging voltage is currently a measure of the robustness of a product. Voltage can be transferred into a current level by evaluating the effective capacitance of a device. A proposal for the alternative CCTLP method is given for defining the stress as a current level based on package parameters. Citation L. Zeitlhoefler, T. Lutz, F. Zur Nieden, K. Esmark and R. Gaertner, "Voltage to Current Correlation for CDM Testing," 2023 45th Annual EOS/ESD Symposium (EOS/ESD), Riverside, CA, USA, 2023, pp. 1-11, doi: 10.23919/EOS/ESD58195.2023.10287735. Voltage to Current Correlation for CDM Testing | IEEE Conference Publication | IEEE Xplore © 2023 EOS/ESD Association, Inc. Reprinted from 2023 EOS/ESD Symposium. Die-to-Die ESD Discharge Current Analysis Abstract: SoC can contain multiple silicon dies connected by die-to-die interfaces. These interfaces do not require additional on-chip ESD protection, but must survive through frontend and backend processes. In this study, die-to-die discharge current waveforms are analyzed using calculation methods for estimating ESD protection targets for the internal interfaces.
Citation P. Tamminen and T. Viheriäkoski, "Die-to-Die ESD Discharge Current Analysis," 2023 45th Annual EOS/ESD Symposium (EOS/ESD), Riverside, CA, USA, 2023, pp. 1-11, doi: 10.23919/EOS/ESD58195.2023.10287764. Die-to-Die ESD Discharge Current Analysis | IEEE Conference Publication | IEEE Xplore © 2023 EOS/ESD Association, Inc. Reprinted from 2023 EOS/ESD Symposium. Distributed Protection for High-Speed Wireline Receivers Abstract: An ESD analysis is carried out for bandwidth extension circuits composed of three inductor segments and integrated with distributed ESD protection. The tri-coil bandwidth extension circuit is proposed for wireline receivers. TLP and S-parameter measurements are used to benchmark the tri-coil’s performance against that of a more conventional T-coil. Citation M. Drallmeier and E. Rosenbaum, "Distributed Protection for High-Speed Wireline Receivers," 2023 45th Annual EOS/ESD Symposium (EOS/ESD), Riverside, CA, USA, 2023, pp. 1-9, doi: 10.23919/EOS/ESD58195.2023.10287739. Distributed Protection for High-Speed Wireline Receivers | IEEE Conference Publication | IEEE Xplore © 2023 EOS/ESD Association, Inc. Reprinted from 2023 EOS/ESD Symposium. 2023 IEEE Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMC+SIPI) ESD Behavior of RF Switches and Importance of System Efficient ESD Design Abstract: RF switches are typically used in the RF front-end of portable devices such as antenna or matching tuners to improve the RF link performance. They are usually the first active devices after the antenna and are vulnerable to primary or secondary ESD discharges to the antennas. This paper investigates the ESD behavior of one of the high frequency switches used in the RF-front-end of portable devices and expresses the importance of the ESD pulse that passes through the switch and reaches the next stage in the RF path, possibly damaging the next stage. Citation S. M. Mousavi et al., "ESD Behavior of RF Switches and Importance of System Efficient ESD Design," 2023 IEEE Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMC+SIPI), Grand Rapids, MI, USA, 2023, pp. 504-509, doi: 10.1109/EMCSIPI50001.2023.10241687. ESD Behavior of RF Switches and Importance of System Efficient ESD Design | IEEE Conference Publication | IEEE Xplore © 2023 IEEE. Reprinted, with permission, from 2023 IEEE Symposium on Electromagnetic Compatibility & Signal/Power Integrity.
2023 International Electron Devices Meeting (IEDM) ESD Challenges in 300nm Si Substrate of DTCO/STCO Scaling Options Abstract: In the design-technology co-optimization (DTCO) and system-technology co-optimization (STCO) scaling era, sub-μm Si substrate has been inevitable for the decent vertical connections. This work, for the first time, evaluates the ESD performance of various ESD devices, including ESD diodes and MOSFET-based ESD devices, with extremely thinned wafer thickness of 300nm and double-sided connectivity. The detriment of the wafer thinning has been assessed for these ESD devices with different key design parameters. Furthermore, the thermal dissipation of these ESD devices with active back-side (BS) contact and metals has been investigated for a possible solution to the thermal issue resulting from the extremely thinned Si substrate. Citation W.-C. Chen, S.-H. Chen, A. Veloso, K. Serbulova, G. Hellings and G. Groeseneken, "ESD Challenges in 300nm Si Substrate of DTCO/STCO Scaling Options," 2023 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2023, pp. 1-4, doi: 10.1109/IEDM45741.2023.10413663. ESD Challenges in 300nm Si Substrate of DTCO/STCO Scaling Options | IEEE Conference Publication | IEEE Xplore © 2023 IEEE. Reprinted, with permission, from 2023 International Electron Devices Meeting. ESD HBM 3kV Discharge for Monolithic GaN-on-Si HEMTs Integrated Chips Abstract: This paper proposes an electrostatic discharge (ESD) protection in Gallium Nitride (GaN)-onsilicon processes. With well-designed ESD circuits, the drawback of large quiescent current (I Q ) in conventional ESD schemes can be reduced through an area-efficient implementation. In addition, the geometry of GaN devices, specifically the lengths of PGaN (L g ), field plate (FP), and gate shield layer (L_M0), can be tuned to effectively reduce the intrinsic gate-to-drain capacitance (C GD ), by tuning the distance from drain to source (L DS ) effectively reduces the on-resistance (R on ). Therefore, the reduction of RC delay greatly improves the response time of the ESD circuit even under low I Q operation. Experimental results show that human body model (HBM) test and machine model (MM) test can be increased to 3kV and 100V, respectively. Moreover, I Q can be reduced to 8.11μA, which is a 222x improvement. Citation T. -W. Wang et al., "ESD HBM 3kV Discharge for Monolithic GaN-on-Si HEMTs Integrated Chips," 2023 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2023, pp. 1-4, doi: 10.1109/IEDM45741.2023.10413733. ESD HBM 3kV Discharge for Monolithic GaN-on-Si HEMTs Integrated Chips | IEEE Conference Publication | IEEE Xplore © 2023 IEEE. Reprinted, with permission, from 2023 International Electron Devices Meeting. Poly-Bounded Silicon-Controlled-Rectifier for ESD Protection in FinFET Technology Abstract: A low-capacitance, low trigger voltage, and fast turn-on silicon-controlled rectifier (SCR) is developed for electrostatic discharge (ESD) protection of 10 circuits in a FinFET process technology. The SCR includes a deep N-well (DNW) for ground isolation, and a DNW biasing technique is introduced to significantly reduce both the DC current leakage and the parasitic capacitance. The advantages of using
poly gates instead of shallow-trench isolation (STI) to separate the anode and cathode of the SCR are characterized through very-fast transmission line (VFTLP) measurements. The proposed SCR device can sink more than 10-A of VFTLP current at 5 V and with less than 80-fF of capacitive loading. Citation S. Huang, S. Parthasarathy, Y. Zhou, J. Hajjar and E. Rosenbaum, "Poly-Bounded Silicon-ControlledRectifier for ESD Protection in FinFET Technology," 2023 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2023, pp. 1-4, doi: 10.1109/IEDM45741.2023.10413765. Poly-Bounded Silicon-Controlled-Rectifier for ESD Protection in FinFET Technology | IEEE Conference Publication | IEEE Xplore © 2023 IEEE. Reprinted, with permission, from 2023 International Electron Devices Meeting. 2024 International Symposium on Physical & Failure Analysis of Integrated Circuits (IPFA) ESD and Latch-up Design Verification Challenges in Packaged Parts and Modules Abstract: ESD and latch-up stress testing to meet industry standards is performed on packaged parts and modules. However, ESD and latch-up design verification has been historically done on die / silicon database. In case of inadequate protection, ESD and latch-up damage occurs on silicon. However, package and module configurations play a significant role. Packages and modules based on the same silicon die can have very different ESD and latch-up protection levels. In this paper we review package and module properties impacting ESD and latch-up protection. These properties include package and module size, capacitance, package wire connectivity and inductance. We discuss ESD and latch-up EDA challenges in packaged parts and modules. We propose a new verification flow to access ESD and latchup on package and module levels as well as outline the implementation steps. Citation M. Khazhinsky, M. Harb and K. -H. Meng, "ESD and Latch-Up Design Verification Challenges in Packaged Parts and Modules," 2024 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, Singapore, 2024, pp. 1-5, doi: 10.1109/IPFA61654.2024.10691018. ESD and Latch-Up Design Verification Challenges in Packaged Parts and Modules | IEEE Conference Publication | IEEE Xplore © 2024 IEEE. Reprinted, with permission, from 2024 International Symposium on Physical & Failure Analysis of Integrated Circuits. Design Optimization of Stacked-NMOS ESD Protection for Mixed-Voltage Application Abstract: In this study, we optimized the stacked-NMOS design in 0.13 μm BCD technology to improve ESD performance and overvoltage tolerance. This was achieved by modifying the N + drain junction to reduce the electric field at the poly/drain overlap region and ensure a more uniformly and deep total current distribution. Citation K. Hwang, T. Yang, J. Zeng, Ajay, G. Zhang and T. Chen, "Design Optimization of Stacked-NMOS ESD Protection for Mixed-Voltage Application," 2024 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, Singapore, 2024, pp. 1-5, doi: 10.1109/IPFA61654.2024.10690872.
Design Optimization of Stacked-NMOS ESD Protection for Mixed-Voltage Application | IEEE Conference Publication | IEEE Xplore © 2024 IEEE. Reprinted, with permission, from 2024 International Symposium on Physical & Failure Analysis of Integrated Circuits. Analysis of the Influence of Pin Position on CDM Peak Current Based on 2.5D and 2D Packaging Abstract: The trend and principle for the variation of Charged Device Model(CDM) peak current of IO and PG pins with pin position in 2.5D CoWoS(50 × 50mm) and 2D FCBGA(45 × 45mm) packaging are analyzed in this work. Pin position has an important effect on the CDM peak current, the closer to the packaging center, the higher peak current of CDM. Moreover, the peak current of the CDM depends on the total charge in the first CDM pulse(Q) and full width at half maximum time of the first CDM pulse(Td), and the trend of CDM peak current with pin position is primarily influenced by parasitic resistance for 10(InputOutput) pins and capacitance for PG(Power and Ground) pins. Furthermore, the CDM peak current of the PG pin is generally higher than that of the IO pin, as the discharge time of the IO pin is much longer than that of the PG pin, which further indicates that the parasitic resistance of the IO pin is larger than that of the PG pin. Therefore, the influence of the pin position should be considered when designing ESD protection circuits to avoid CDM-related failures caused by ESD underdesign. Citation M. Wang et al., "Analysis of the Influence of Pin Position on CDM Peak Current Based on 2.5D and 2D Packaging," 2024 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, Singapore, 2024, pp. 1-4, doi: 10.1109/IPFA61654.2024.10690911. Analysis of the Influence of Pin Position on CDM Peak Current Based on 2.5D and 2D Packaging | IEEE Conference Publication | IEEE Xplore © 2024 IEEE. Reprinted, with permission, from 2024 International Symposium on Physical & Failure Analysis of Integrated Circuits. The Effect of the P-Substrate Connection on the HBM Robustness of P-Type ESD Device Abstract: Although the p-substrate connection of p-type ESD device does not have any impact on the device's It2 while connecting the p-substrate to the ground degrades the human-body model (HBM) robustness of the device significantly. From the experiment results, adding N-type buried layer (NBL) to ptype ESD device can have the device HBM robustness invariant to the p-substrate connection. Based on the T-CAD simulations, the effect of the p-substrate connection on the HBM robustness of p-type ESD device is revealed in this paper. As HBM raises up the potential of the whole region of p-type ESD device after the onset of zapping for a while and then the high potential region of the device decreases with decreasing HBM current if the p-substrate is grounded, resulting in the current crowding. On the contrary, the high potential region of p-type ESD device does not decrease with decreasing HBM current if the psubstrate is floating or NBL is added to the device, resulting in the uniform current distribution. Citation J. -H. Lee et al., "The Effect of the P-Substrate Connection on the HBM Robustness of P-type ESD Device," 2024 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, Singapore, 2024, pp. 1-8, doi: 10.1109/IPFA61654.2024.10691149.
The Effect of the P-Substrate Connection on the HBM Robustness of P-type ESD Device | IEEE Conference Publication | IEEE Xplore © 2024 IEEE. Reprinted, with permission, from 2024 International Symposium on Physical & Failure Analysis of Integrated Circuits. ESD Characteristics Improving of LVTSCR by Adding RC Triggering Circuit in 0.18 μm BCD Technology Abstract: In this paper, Low Voltage Triggering SCR (LVTSCR) and RC-triggered LVTSCR are fabricated in a 0.18 μm Bipolar-CMOS-DMOS (BCD) process. TCAD simulation is introduced to study the ESD protection devices' working mechanism, while transmission line pulse (TLP) measuring system being used to characterize the devices' Electrostatic Discharge (ESD) characteristics. It is verified that the additional RC triggering circuit can reduce the devices' trigger voltage, and better ESD characteristics with higher holding voltage can be obtained through altering certain critical size. Citation Y. Wang, S. Ji, S. Li, H. Yang and X. Chen, "ESD Characteristics Improving of LVTSCR by Adding RC Triggering Circuit in 0.18 μm BCD Technology," 2024 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, Singapore, 2024, pp. 01-06, doi: 10.1109/IPFA61654.2024.10691125. ESD Characteristics Improving of LVTSCR by Adding RC Triggering Circuit in 0.18 μm BCD Technology | IEEE Conference Publication | IEEE Xplore © 2024 IEEE. Reprinted, with permission, from 2024 International Symposium on Physical & Failure Analysis of Integrated Circuits. Automotive Electronics EOS Failure Analysis and Diagnosis Abstract: Automobile industry has dramatically changed over past two decades. All OEMs start to integrate more IC components and implement high-end technology functions. Among automotive electronics failure, EOS related issue always takes the highest failure rate. This paper identifies failure analysis of component ESD failure, board level and system level EOS failure. Related diagnosis process and root cause identification are also shared. Citation S. Wang, Y. Liu and H. Bai, "Automotive Electronics EOS Failure Analysis and Diagnosis," 2024 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, Singapore, 2024, pp. 01-05, doi: 10.1109/IPFA61654.2024.10691106. Automotive Electronics EOS Failure Analysis and Diagnosis | IEEE Conference Publication | IEEE Xplore © 2024 IEEE. Reprinted, with permission, from 2024 International Symposium on Physical & Failure Analysis of Integrated Circuits.
Study of Efficient Design on Latchup in 130nm BCD Technology for High Voltage Application Abstract: We studied efficient design for high external latchup (ELUP) robustness in 130nm BCD technology under different Deep-Trench-Isolation (DTI) and N-EPI pickup configurations (NCOMP). We show DTI is very effective in reducing the space between I/O injector device and sensitive logic device, which is an ideal requirement for a lower footprint design with high latchup robustness. Furthermore, we demonstrate the critical role of DTI, when NCOMP around high voltage (HV) I/O FETs is biased at 0V, in latchup robustness of power management designs. Citation A. Rebello et al., "Study of Efficient Design on Latchup in 130nm BCD Technology for High Voltage Application," 2024 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, Singapore, 2024, pp. 1-4, doi: 10.1109/IPFA61654.2024.10691056. Study of Efficient Design on Latchup in 130nm BCD Technology for High Voltage Application | IEEE Conference Publication | IEEE Xplore © 2024 IEEE. Reprinted, with permission, from 2024 International Symposium on Physical & Failure Analysis of Integrated Circuits. The Influence of Gate-Series-Resistor on the ESD Protection and Switching Speed for 650V GaNHEMT Circuit Abstract: Unlike CMOS technology, there only exist two components, HEMT and resistor, that can be used to design as the electrostatic-discharge (ESD) protection circuit in GaN technology. Although HEMT has very robust ESD capability, it still cannot work very well without the resistor to clamp the ESD current or pull up the gate voltage to turn on its channel. So, most ESD protection circuits for protected HEMT are composed of resistor and HEMT. In general, the protection capability of an ESD protection circuit is determined by the size of ESD HEMT and the resistor resistance. However, the high-resistance resistor degrades the switching speed of protected HEMT, while the low-resistance resistor degrades the protection capability of ESD protection circuit. In this paper, how the turn-on gate resistor (Rg ON ) affects the protection capability of all-terminal ESD protection circuit for a 650V GaN HEM is studied. From the test results, this protection circuit is demonstrated that can protect the gate of protected HEMT against 1 kV HBM strike for any zapping condition even if the Rg ON is only 2ohm. Citation J. -H. Lee et al., "The Influence of Gate-Series-Resistor on the ESD Protection and Switching Speed for 650V GaNHEMT Circuit," 2024 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, Singapore, 2024, pp. 1-6, doi: 10.1109/IPFA61654.2024.10691316. The Influence of Gate-Series-Resistor on the ESD Protection and Switching Speed for 650V GaNHEMT Circuit | IEEE Conference Publication | IEEE Xplore © 2024 IEEE. Reprinted, with permission, from 2024 International Symposium on Physical & Failure Analysis of Integrated Circuits.
2024 International Symposium on Reliability Physics (IRPS) Load-line Dependent Current Filament Dynamics in Nanoscale SCR Devices Abstract: In this paper physics of experimentally observed abnormal behavior in STI bounded SiliconControlled-Rectifier (SCR) structures is investigated and explained using basic principles and 3D electrothermal TCAD simulations. The SCR device is found to show pulse to pulse instability in the negative resistance (snapback) region during the lOOns pulse width TLP measurement. The instabilities were independent of SCR geometrical design variations but were dependent on the load line conditions used in the TLP measurement. The physical insights and device physics has been explored using well calibrated 3 D process and device TCAD. Citation M. Goyal, M. Chaturvedi, R. Kumar, M. Vaidya and M. Shrivastava, "Load-line Dependent Current Filament Dynamics in N anoscale SCR Devices," 2024 IEEE International Reliability Physics Symposium (IRPS), Grapevine, TX, USA, 2024, pp. 1-6, doi: 10.1109/IRPS48228.2024.10529351. Load-line Dependent Current Filament Dynamics in N anoscale SCR Devices | IEEE Conference Publication | IEEE Xplore © 2024 IEEE. Reprinted, with permission, from 2024 International Symposium on Reliability Physics. Missing Trigger Circuit Action and Device Engineering for Conventional Nanoscale SCR Abstract: In this work co-optimization of silicon-controlled rectifier (SCR) ESD characteristics with its low voltage trigger circuit is presented. Resistance and Capacitance (RC) controlled thick gate NMOS and PMOS based circuits have been explored and compared. The design approach is discussed and presented for low trigger SCR for two different trigger circuits. In the process we find that some of the trigger circuits previously reported in literature do not work as desired until co-optimized device engineering techniques are used. The circuit insights are explored using well calibrated electrothermal 3D process and device TCAD mixed mode simulations. Citation M. Goyal, M. Chaturvedi, R. Kumar, M. Vaidya and M. Shrivastava, "Missing Trigger Circuit Action and Device Engineering for Conventional Nanoscale SCR," 2024 IEEE International Reliability Physics Symposium (IRPS), Grapevine, TX, USA, 2024, pp. 1-6, doi: 10.1109/IRPS48228.2024.10529418. Missing Trigger Circuit Action and Device Engineering for Conventional Nanoscale SCR | IEEE Conference Publication | IEEE Xplore © 2024 IEEE. Reprinted, with permission, from 2024 International Symposium on Reliability Physics. Reduced RC Time Constant High Voltage Tolerant Supply Clamp for ESD Protection in 16nm FinFET Technology Abstract: This work presents an active feedback-based high voltage tolerant (5 V) supply clamp for ESD protection in 16-nm FinFET CMOS technology. The proposed trigger circuit biases the BigFETs for maximum ESD robustness and employs positive feedback to maintain the clamp in the on-state such that the clamp can shunt the ESD current for the duration of an HBM event. Negative feedback circuitry is
employed to turn the clamp off in case of mistriggering. The clamp is shown to be capable of discharging up to 4-kV HBM current. Citation S. Huang, S. Parthasarathy, Y. Zhou, J. -J. Hajjar and E. Rosenbaum, "Reduced RC Time Constant High Voltage Tolerant Supply Clamp for ESD Protection in 16nm FinFET Technology," 2024 IEEE International Reliability Physics Symposium (IRPS), Grapevine, TX, USA, 2024, pp. 1-7, doi: 10.1109/IRPS48228.2024.10529384. Reduced RC Time Constant High Voltage Tolerant Supply Clamp for ESD Protection in 16nm FinFET Technology | IEEE Conference Publication | IEEE Xplore © 2024 IEEE. Reprinted, with permission, from 2024 International Symposium on Reliability Physics. An Analysis of CDM-Induced BTI-like Degradation using VF-TLP in Advanced FinFET Technology Abstract: The electrostatic discharge (ESD) phenomenon is a critical reliability concern, and the charged device model (CDM) is well known for its relatively high voltage peak with few nanoseconds duration on the gate oxide (GOX), resulting in breakdown. However, as ESD design window shrinks, even GOX degradation before hard breakdown during component-level CDM qualification can cause reliability issues such as soft-failures. This degradation can be attributed to the quickly increased electric field on the GOX, leading to the rapid creation of trapped charges before catastrophic damage. This study analyzes CDMinduced bias temperature instability (BTI)-like degradation and models threshold voltage (Vth) shift using a very-fast transmission line pulse (VF-TLP) with 1ns pulse width and 200ps rise and fall time, generally proposed for CDM evaluation. The experiment was conducted with various VF-TLP voltage peaks, numbers of pulsing iterations and GOX areas. And, finally, Vth shift model considering statistical variation is presented. This model can be a guideline to prevent CDM-induced GOX degradation at an early design stage. Citation S. Oh et al., "An Analysis of CDM-induced BTI-like Degradation using VF-TLP in Advanced FinFET Technology," 2024 IEEE International Reliability Physics Symposium (IRPS), Grapevine, TX, USA, 2024, pp. 1-5, doi: 10.1109/IRPS48228.2024.10529338. An Analysis of CDM-induced BTI-like Degradation using VF-TLP in Advanced FinFET Technology | IEEE Conference Publication | IEEE Xplore © 2024 IEEE. Reprinted, with permission, from 2024 International Symposium on Reliability Physics. On-Chip Single-Shot Pulse Generator for TDDB Characterization on a Sub-Nanosecond Timescale Abstract: During charged device model (CDM) electrostatic discharge (ESD) events, MOSFET gate oxides may be exposed to high voltage stress lasting for a few hundred picoseconds or less, and the gate oxide breakdown voltage is an important parameter for ESD designers. This work presents an on-chip pulse generator fabricated in a 65-nm CMOS process capable of producing clean single-shot pulses with amplitude up to 6 V and pulse width as short as 200 ps. The pulse generator is used for an experimental investigation of MOS gate oxide breakdown voltage on a sub-ns timescale and to assess the validity of the power-law model.
Citation M. Drallmeier, Y. Zhou and E. Rosenbaum, "On-Chip Single-Shot Pulse Generator for TDDB Characterization on a Sub-Nanosecond Timescale," 2024 IEEE International Reliability Physics Symposium (IRPS), Grapevine, TX, USA, 2024, pp. 8C.4-1-8C.4-10, doi: 10.1109/IRPS48228.2024.10529361. On-Chip Single-Shot Pulse Generator for TDDB Characterization on a Sub-Nanosecond Timescale | IEEE Conference Publication | IEEE Xplore © 2024 IEEE. Reprinted, with permission, from 2024 International Symposium on Reliability Physics. 2024 Symposium on VLSI Technology Toward 0 V ESD Protection in 2.5D/3D Advanced Bonding Technology Abstract: This paper presents a methodology to help prevent overdesign of Electrostatic Discharge (ESD) protection circuits for internal I/O in 2.5D/3D bonding technologies. We explore how the voltage suppression effect mitigates voltage-driven gate oxide breakdown during stacking and emphasize the role of series resistance in reducing peak discharge current. Our findings indicate that highly variable noncontact discharges are not a concern in advanced bonding technologies, shifting the focus to more predictable contact discharges. Also, we provide guidelines to design efficient ESD protection circuits for internal IO in 2.5D/3D stacked system. Citation S. . -H. Lin et al., "Toward 0 V ESD Protection in 2.5D/3D Advanced Bonding Technology," 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, HI, USA, 2024, pp. 1-2, doi: 10.1109/VLSITechnologyandCir46783.2024.10631467. Toward 0 V ESD Protection in 2.5D/3D Advanced Bonding Technology | IEEE Conference Publication | IEEE Xplore © 2024 IEEE. Reprinted, with permission, from 2024 Symposium on VLSI Technology. 2024 International Conference on VLSI Design MLESD: Machine Learning Assisted Faster On-Chip ESD Convergence Strategy Abstract: As technology advancement continues beyond the sub-10 nm process node, modern highfrequency designs are more prone to damage due to electrostatic discharge (ESD) effects. Protecting a device from an ESD event is one of the major reliability aspects of any modern SoC implementation. The current industry practice is to place the ESD clamp cells in the design and connect them with the power and ground bumps using a lower resistance such that most of the transient current will pass through the low-resistance path. To ensure the ESD resistance is lesser than the resistance through the logic cell, designers used to perform a time-intensive ESD simulation after every design modification with respect to the ESD requirements in industry-standard EDA tools, which delays the overall ESD convergence process. In order to address this problem, Machine Learning (ML) techniques are adopted in this research to reduce the number of simulation cycles. Relevant features are identified, and a number of regression algorithms are explored for ML training. The XGBOOST regressor is selected as the best trained model. On the inference dataset, predicted ESD resistance has a very good correlation (R2score>0.99) with the sign-off accurate simulation result. With the fast and almost accurate prediction of ESD resistance, designers can now opt for the detailed simulation intermittently over the
ESD convergence process based on time availability. This can lead to more than two weeks of left-shift in the ESD convergence process. Citation S. Nishad, S. Kundu, N. Richaud, S. Mallikarjun, M. Prasad and L. Renker, "MLESD: Machine Learning Assisted Faster On-Chip ESD Convergence Strategy," 2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID), Kolkata, India, 2024, pp. 281-286, doi: 10.1109/VLSID60093.2024.00053. MLESD: Machine Learning Assisted Faster On-Chip ESD Convergence Strategy | IEEE Conference Publication | IEEE Xplore © 2024 IEEE. Reprinted, with permission, from 2024 International Conference on VLSI Design. 2024 IEEE Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMC+SIPI) A Model for Corona Streamer Propagation on Glass during an Air Discharge Abstract: Corona discharge to a glass surface is challenging to model due to a poorly understood air and surface ionization process. A modeling methodology based on the transmission line modeling (TLM) approach is proposed to simulate the streamer propagation process. The time-changing corona streamer resistance is estimated using the Rompe and Weizel spark model. The streamer is represented using small segments consisting of the arc resistance, per unit length (PUL) capacitance of the streamer, PUL inductance, a switch representing streamer formation, and a surface discharge gap voltage representing the voltage drop caused by ions within the streamer length. The propagation of the corona streamer depends on the tangential electric field strength at the streamer tip being higher or lower than the breakdown threshold for streamer formation. This preliminary 1D model shows plausible results for the current waveform shape, Lichtenburg dust figure diameter and streamer propagation velocity for a positive surface discharge to the glass. Although the model requires further improvement to predict propagation of multiple corona streamers, it provides a basis for simulation of a corona discharge on a glass surface which is related to the behavior of the underlying physics. Citation Z. Peng, J. Zhou, D. Kostka, D. Pommerenke and D. Beetner, "A Model for Corona Streamer Propagation on Glass During an Air Discharge," 2024 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI), Phoenix, AZ, USA, 2024, pp. 284-289, doi: 10.1109/EMCSIPI49824.2024.10705511. A Model for Corona Streamer Propagation on Glass During an Air Discharge | IEEE Conference Publication | IEEE Xplore © 2024 IEEE. Reprinted, with permission, from 2024 IEEE Symposium on Electromagnetic Compatibility & Signal/Power Integrity. Metamaterial-Enabled Localization of Electrostatic Discharges using Time Reversal Abstract: Protection against electrostatic discharges requires knowledge of the discharge-current path. Thanks to the time-reversal technique combined with a GHz-range resonant metalens, we present an experimental gateway to imaging subwavelength interference sources.
Citation E. L. Boudec, D. Martinez, N. Mora, M. Rubinstein, F. Vega and I. Yahi, "Metamaterial-enabled localization of electrostatic discharges using time reversal," 2024 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI), Phoenix, AZ, USA, 2024, pp. 290290, doi: 10.1109/EMCSIPI49824.2024.10705638. Metamaterial-enabled localization of electrostatic discharges using time reversal | IEEE Conference Publication | IEEE Xplore © 2024 IEEE. Reprinted, with permission, from 2024 IEEE Symposium on Electromagnetic Compatibility & Signal/Power Integrity. Time-Dependent Resistance-Based Dynamic Behavior Model of Spark Gap Device under ESD Pulse Abstract: This paper investigates the dynamic response characteristics of spark gap structures on printed circuit boards (PCB) under electrostatic discharge (ESD). A gas discharge tube (GDT) is selected as the research subject. Initially, voltage and current signals at the device ports are measured under transmission line pulse (TLP) excitation, and the variation in the time lag of the spark gap structures with different voltage levels is analyzed. Subsequently, a dynamic behavior model, based on a timedependent typical arc resistance model, is developed to predict the response of the GDT to TLP pulses. This system-level model is further validated through experiments using an electrostatic generator excitation. Citation M. Yang, G. Luo, J. Dang, Z. Xue and W. Zhang, "Time-dependent Resistance-based Dynamic Behavior Model of Spark Gap under ESD Pulse," 2024 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI), Phoenix, AZ, USA, 2024, pp. 291-295, doi: 10.1109/EMCSIPI49824.2024.10705469. Time-dependent Resistance-based Dynamic Behavior Model of Spark Gap under ESD Pulse | IEEE Conference Publication | IEEE Xplore © 2024 IEEE. Reprinted, with permission, from 2024 IEEE Symposium on Electromagnetic Compatibility & Signal/Power Integrity. 2024 International Symposium on Electromagnetic Compatibility – EMC Europe Modeling the ESD Dynamic Behavior of TVS Based on a Time-dependent Resistance Abstract: The traditional SPICE diode model does not fully characterize the response of transient voltage suppressor (TVS) under transient electrostatic discharge (ESD) pulses. This paper introduces a dynamic behavior model of the TVS diode under transient voltage, based on a time-dependent resistance model. Drawing on the similarity assumption that the avalanche breakdown behavior between the diode and the gas spark-gap device share physical mechanisms, the time-dependent arc resistance model of gas breakdown is utilized to describe the transient response behavior of TVS devices. Additionally, an extra series resistance is adopted to modify the arc resistance model, ensuring it matches the transient response curve. Consequently, consistency between simulation and measurement is achieved under transmission line pulse (TLP) pulses of varying voltage levels, verifying the accuracy of the model under ESD generator excitation.
Citation J. -F. Dang, G. -X. Luo, W. -D. Zhang and D. Pommerenke, "Modeling the ESD Dynamic Behavior of TVS Based on a Time-dependent Resistance," 2024 International Symposium on Electromagnetic Compatibility – EMC Europe, Brugge, Belgium, 2024, pp. 651-656, doi: 10.1109/EMCEurope59828.2024.10722665. Modeling the ESD Dynamic Behavior of TVS Based on a Time-dependent Resistance | IEEE Conference Publication | IEEE Xplore © 2024 IEEE. Reprinted, with permission, from 2024 International Symposium on Electromagnetic Compatibility – EMC Europe. Transmission Line Based CDM ESD Current Target to Overcome Bandwidth Limitations Abstract: Reducing charged device model (CDM) electrostatic discharge (ESD) target levels for advanced integrated circuits (ICs) and systems on chip (SoCs) enables cost-effective manufacturing. Notably fast rise times, as low as 20 ps, have been observed for CDM events below 250 V. Previous investigations have highlighted fast rise times as critical parameters for damage in CDM testing of devices. These rapid rise times result in spectral frequency content exceeding 17.5 GHz, surpassing the bandwidth of existing CDM current targets employing disk resistors. To overcome this bandwidth limitation, a CDM current target comprised of parallel-connected transmission lines has been developed. Full-wave simulation results confirm the design of an initial prototype. Time-domain measurements conducted in an experimental setup exhibit exemplary results, with potential for further enhancement through deembedding techniques. Citation G. Fellner, D. Pommerenke, L. Zeitlhoefler and F. Z. Nieden, "Transmission Line Based CDM ESD Current Target to Overcome Bandwidth Limitations," 2024 International Symposium on Electromagnetic Compatibility – EMC Europe, Brugge, Belgium, 2024, pp. 640-645, doi: 10.1109/EMCEurope59828.2024.10722655. Transmission Line Based CDM ESD Current Target to Overcome Bandwidth Limitations | IEEE Conference Publication | IEEE Xplore © 2024 IEEE. Reprinted, with permission, from 2024 International Symposium on Electromagnetic Compatibility – EMC Europe. Comparative Analysis of Calibration Procedures in Current and Proposed Editions of the IEC 61000-4-2 Standard Abstract: The IEC 61000-4-2 Standard has been used in the last decades as the main Test Standard for commercial ESD testing extensively. A new edition of this Standard is currently under work and some of its potential changes will affect the ESD generator calibration procedure significantly. In an effort to improve reproducibility between the different calibration laboratories a new waveform parameter is added. In this work, calibration measurements according to the current edition 2 and the proposed edition 3 of IEC 61000-4-2 are carried out for a commercially available ESD generator. The calibration results are presented and the emerged issues are discussed.
Citation P. K. Papastamatis, I. P. Katsanaki, E. P. Nicolopoulou, C. D. Nikolopoulos, C. A. Christodoulou and I. F. Gonos, "Comparative analysis of calibration procedures in current and proposed editions of the IEC 61000-4-2 Standard," 2024 International Symposium on Electromagnetic Compatibility – EMC Europe, Brugge, Belgium, 2024, pp. 483-488, doi: 10.1109/EMCEurope59828.2024.10722155. Comparative analysis of calibration procedures in current and proposed editions of the IEC 61000-4-2 Standard | IEEE Conference Publication | IEEE Xplore © 2024 IEEE. Reprinted, with permission, from 2024 International Symposium on Electromagnetic Compatibility – EMC Europe.
Introduction to Static Control for Roll-to-Roll Manufacturing Kelly Robinson IEEE Life Fellow Electrostatic Answers 15 Piping Rock Runt Fairport, NY 14450, USA Kellly.Robinson@ElectrostaticAnswers.com Abstract -- Roll-to-Roll (R2R) manufacturing is used extensively in printing and flexible packaging industries. These markets exceed $30B annually in the US [1]. Static ignitions injury employees. Electrical charge stored on wound rolls shocks operators and disrupt machine operations. Static causes sheet sticking and sparks damage products. I estimate that injuries, product waste, and machine downtime caused by static electricity exceeds $600M annually (2%) in the US. This human suffering and waste may be eliminated by static control systems. Implementing effective static control on an R2R manufacturing line is a 4-step, data-driven process. First, identify sources of static charging with a static survey. Next, install static dissipaters forming a fault-tolerant static control system. Once static dissipaters are operational, verify that static is well controlled with another, static survey. Finally, maintain static performance by including static control in operations including regularly inspecting static dissipaters and including static control in Management of Change (MoC) procedures. Index Terms— electrostatic analysis, electrostatic processes, hazardous areas, manufacturing processes, plastics industry, safety, sparks I. NOMENCLATURE Parameter Units Description DCore m Roll core diameter DRoll m Wound roll diameter dWeb m Web thickness LWeb m Web length ρVol C/m3 Volumetric charge density σBot C/m2 Surface charge density on the bottom web surface σIn C/m2 Surface charge density on the inside web surface σNet C/m2 Net surface charge density σOut C/m2 Surface charge density on the top web surface σTop C/m2 Surface charge density on the top web surface II. INTRODUCTION With Roll-to-Roll (R2R) manufacturing, products are produced on continuous, flexible, webs. Webs may be formed, for example, by extruding a hot, molten polymer such as polypropylene (PP) onto a chilled roller. The polymer cools and it is stripped from the chilled roller forming a continuous, flexible web. At the end of the formation or casting line, webs are wound into rolls to be delivered to subsequent manufacturing operations including printing, coating, lamination (forming a single web from two incoming webs), and slitting (cutting the web lengthwise into multiple, narrower webs). While I use the terms web and film interchangeable, web is the more general term while film often refers to a web with a specific formulation or coating. Products produced by R2R manufacturing include flexible packaging (e.g., zip-lock bags, heat-sealed bags), and labels. In these R2R manufacturing operations, static electricity presents hazards to employees, product quality, and production operations. When insulating webs such as polypropylene (PP) or polyethylene terephthalate (PET) are conveyed through solvent coaters or printing operations using ignitable inks, static sparks from these webs can ignite solvent vapors. Static charges stored on winding rolls can shock operators. The sparks from wound rolls can be over two feet long causing shock requiring hospitalization, or worse. Even lower energy shocks can cause reactions that result in falls and other secondary injuries. Static sparks can damage thin coating such a silicone release layers or other sensitive coatings having chemical or electronic functionality. Static charges on films attracted airborne contaminates particularly during slitting and punching operations. These static issues cause human suffering and economic harm. R2R manufacturing is big business with revenues exceeding $30B USD annually in the US [1]. I estimate that the cost of injuries and waste caused by static is on the order of 2% exceeding $600 M USD annually in the US. Eliminating human suffering and reducing waste motivates initiatives to improve static performance in R2R manufacturing operations. Efforts to improve the static performance of manufacturing operations has been evolving at least since 1904 when William Chapman patented a method of removing static electricity from paper and yarn [2]. US Patent 777,598 reads as follows. Static electricity generated by friction and by the separation of surfaces is often the source of great annoyance and delay in the operations of various kinds of machinery – as, for instance, in the calenders of paper-machines, in printing-presses, and in the machinery for working different kinds of fabrics – and it becomes of great importance to 2021 IEEE Industry Applications Society Annual Meeting (IAS) | 978-1-7281-6401-4/21/$31.00 ©2021 IEEE | DOI: 10.1109/IAS48185.2021.9677304
neutralize these static charges in order that the machinery may be worked in an efficient manner and at a desirable rate of speed. In the handling of paper, the sheets of paper stick to each other and to other surfaces, causing breakage and delay, and to prevent these difficulties, a variety of devices have been tried in the past with unsatisfactory results. These comments apply to our present day R2R operations. III. OVERVIEW OF STATIC CONTROL TABLE I 4-STEP DATA-DRIVEN PROCESS 1. Identify static charging sources. 2. Install static dissipaters. 3. Verify static performance. 4. Maintain static performance. Use the 4-step process in Table 1 to implement an effective static control system. A. Identify Static Charging Sources Identifying sources of static charging is key to effective control as discussed in IV. Static Control System Design. These sources of static charging may be identified by making a sequence of electrostatic fieldmeter (ESFM) measurements along the material flow from incoming materials to finished products. Fig. 1. Electrostatic charge on a web may be on the top surface, on the bottom surface, or within the volume of the web. An ESFM responds to the net charge density σNet on the web. The net charge density in (1) is the sum of all charges on the web. Net Top Bot Vol Web d σ σ σ ρ = + + (1) Normally, the volumetric charge density ρVol in a web is minimal. Static charges are primarily on the web surfaces. A change from one ESFM reading to the next indicates a change in the amount of static charge on the web. A source of static charging somewhere between the two measurements deposited static on the web. B. Install Static Dissipaters Each static dissipater achieves a specific goal. Each dissipater requires maintenance and verification. Achieving the needed system performance using the fewest number of dissipaters minimizes operational burden. Install static dissipaters first to protect high risk areas such as solvent coaters and winding rolls. Historically, static control was pursued by protecting high-risk areas. While this approach is effective, it is prone to failures. A static dissipater failure places a high-risk area at peril. Fault-tolerant control is achieved by also neutralizing static at sources of static charging. With effective source control, the webs entering high-risk areas should be nearly charge-free making the static dissipaters protecting these areas a redundant, second layer of protection. C. Verify static performance Fig. 2. While the ESFM responds to all of the charge inside CV, the ESVM responds only to the charge density on the exposed, top surface Once static dissipaters are installed and operational, perform a static survey using both ESFMs and electrostatic voltmeters (ESVMs). While the ESFM in Fig 2 responds to the net charge density σNet as in (1), the ESVM responds to the charge density only on the exposed, top surface. Using both an ESFM and an ESVM, the charge density σTop and σBot can both be measured to ensure that the charge densities on both web surfaces are properly controlled. D. Maintain static performance Static problems occur when two elements in the faulttolerant control system fail simultaneously. Our process monitoring and system maintenance must detect a failure and restore operation of a failed component before two failures occur. IV. STATIC CONTROL SYSTEM DESIGN Fault-tolerant static control systems maintain satisfactory static control even when any single system element fails. Fault-tolerant control is achieved with redundancy. However, each static dissipater requires maintenance and verification. Using fewer static dissipaters reduces maintenance and verification. A. Protect High Risk Areas Fig. 3. The threat (static charges) penetrates to the high-risk area (winding roll) only when two system components fail simultaneously.
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