MayJune 2011

The ESD Association newsletter, published for everyone with an interest in the understanding and control of electrostatic discharge. Volume 27, No. 3 May/June 2011 In this issue THRESHOLD TM From the President, page 2 BoD Nominations, pages 3-6 Education, pages 7-8 ESD On Campus, page 9 Volunteer Spotlight, page 10 Tech Talk, page 11 Standards Meeting Schedule, page 12 Symposium, pages 13-14 Q&A, page 14 University Grant, pages 15-16 ESD On Campus Program, page 17 Corporate Sponsor Program, page 18 Local Sparks, page 19 Calendar, page 20 Photo Corner, page 21 Symposium Program Now Available! Visit the Association web site www.esda.org to download your 2011 Symposium program and registration guide. 1 September 11-16, 2011 Disneyland Hotel Anaheim, CA The International Technical Forum on Electrical Overstress and Electrostatic Discharge 33 rD AnnuAl EOS/ESD SympOSIum & ExHIbITS Sponsoredby theESDAssociation incooperationwith the IEEE. Technicallyco-sponsoredby theElectronDevicesSociety. ESD Device Design Essentials June 13-14, 2011 Sheraton Mission Valley San Diego Hotel, San Diego, CA Instructors: Gianluca Boselli, Texas Instruments; Michael G. Khazhinsky, Silicon Labs This two-day seminar consists of concentrated versions of twelve ESDA tutorials which comprise the ESDA Device Design Certification Program. • ESD On-Chip Protection in Advanced Technologies • SPICE-Based ESD Protection Design Utilizing Diodes and Active MOSFET Rail Clamp Circuits • EOS/ESD Failure Models and Mechanisms • On-Chip ESD Protection in RF Technologies • Charged Device Model Phenomena and Design • Latch-up Physics and Design • Circuit Modeling and Simulation for On-Chip Protection • Troubleshooting On-Chip ESD Failures • Device Testing–IC Component Level: HBM, CDM, MM, and TLP • Impact of Technology Scaling on ESD High Current Phenomena and Implications for Robust ESD Design • Transmission Line Pulse Measurements: Parametric Analyzer for ESD On- Chip Protection • System Level ESD/EMI: Testing to IEC and other Standards PART III (8:00 AM-Noon) This part describes special ESD de- sign cases, including Charged Device Model (CDM) phenomena and design and on-chip ESD protection in RF Technologies. PART IV (1:00 PM-5:00) The final section discusses latch-up, EOS/ESD failure models and mecha- nisms. The seminar concludes with practical examples for troubleshooting of on-chip ESD failures. Day 2 June 14 PART I (8:00 AM-Noon) This part reviews the fundamentals of ESD testing, high-current physics, and ESD modeling. The focus is on device- level (HBM, CDM, MM, TLP) and sys- tem level testing, impact of technology scaling on ESD high current phenom- ena, as well as, circuit modeling and simulation for on-chip protection. PART II (1:00 PM-5:00) The principles from part I are then ap- plied to ESD Protection Design. Part II describes ESD on-chip protection in advanced technologies, SPICE- based ESD protection design utilizing diodes and active MOSFET rail clamp circuits, etc. Day 1 June 13 New Seminar