EOS/ESD Association, Inc. Acronyms

A

  • AHE

    Automated handling equipment

  • ANSI

    American National Standards Institute

  • APD

    Anti-parallel diodes

  • ASTM

    American Society for Testing and Materials

  • ASTM

    American Society for Testing and Materials

B

  • BCM

    Body contacting mechanism

  • BCP

    Body contact point

C

  • CAFÉ

    Constant area and force electrode

  • CBE

    Charged body event

  • CDE

    Cable discharge event

  • CDM

    Charged device model

  • CPM

    Charged plate monitor

  • CTI

    Components Technology Institute, Inc.

  • CUT

    Component under test

D

  • DIN

    Deutsches Institut fur Normung

  • DRC

    Design rule check

  • DUT

    Device under test

E

  • EDA

    Electronic design automation

  • EGC

    Equipment grounding conductor

  • EMI

    Electromagnetic imaging

  • EMI

    Electromagnetic interference

  • EOS

    Electrical overstress

  • EPA

    ESD protected area

  • ERC

    Electrical rule check

  • ESA

    Electrostatics Society of America

  • ESD

    Electrostatic Discharge

  • ESDS

    Electrostatic discharge sensitivity

  • ESDS

    Electrostatic discharge susceptibility

  • eut

    Equipment under Test

F

  • FCS

    Floor contacting surface

  • FP

    Field plate

  • FWHM

    Full Width at Half Maximum

G

  • GP

    Ground plane

  • GSA

    Global Semiconductor Alliance

  • Gtp

    Ground termination point

H

  • HBM

    Human body model

  • HMM

    Human metal model

I

  • IC

    Integrated Circuit

  • IDD / ISS

    Supply / ground current

  • IDDNOM

    Nominal supply current

  • IDDNOM

    Nominal supply current

  • IDEMA

    International Disk Drive Equipment and Materials Association

  • IDM

    Integrated device manufacturer

  • IEC

    International Electrotechnical Commission

  • IEEE

    Institute of Electrical and Electronics Engineers

  • IEST

    Institute of Environmental Sciences and Technology

  • iNARTE

    National Association of Radio and Telecommunications Engineers

  • IP

    Intellectual property

  • IPC

    Association Connecting Electronic Industries

  • ISO

    International Organization for Standardization

  • ISTRESSMAX

    Stress current limit

J

  • JEDEC

    Solid State Technology Association, formerly known as the Joint Electron Device Engineering Council

L

  • LDMOS

    Laterally diffused MOS

  • LVDS

    Low voltage differential signaling

M

  • MCM

    Multi-chip modules

  • MM

    Machine model

O

  • OVT

    Over-Voltage Tolerant circuit design

P

  • PCELL

    Parameterized cell

  • PUT

    Port under Test

R

  • Rbus

    Bus resistance

  • Rcrit

    Critical resistance

  • RDL

    Redistribution layer

  • RFPP

    RF pin pairs

  • Rpgp

    Resistance point-to-groundable point

  • Rpp

    Resistance point-to-point

  • Rtg

    Resistance Top to Ground

  • Rtt

    Resistance Top to Top

S

  • S

    Standard

  • SCR

    Silicon controlled rectifier

  • SDM

    Socketed device model

  • SMTA

    Surface Mount Technology Association

  • SOA

    Safe operation area

  • SoC

    System on chip

  • SP

    Standard practice

  • SSPP

    Special signal pin pairs

  • STDCOM

    Standards Committee

  • STM

    Standard test method

T

  • TAS

    Technical Advisory Support Committee

  • TCAD

    Technology computer-aided design

  • TDR

    Time domain reflectometer

  • TDRT

    Time domain transmission and reflection

  • TDT

    Time domain transmission

  • TFB

    Test fixture board

  • TLP

    Transmission line pulse

  • TR

    Technical report

U

  • UPA

    Unprotected area

V

  • VBM

    Vote-by-Mail

  • VDD

    Supply voltage

  • VDMOS

    Vertical diffused MOS

  • VF-TLP

    Very fast transmission line pulse