ESD Design Engineer Certification 2 (EDEC2)

Registration

Initiate an official file in your name at EOS/ESD Association, Inc. headquarters. Register Online

Complete Required Minimum Prerequisite Courses

The courses are listed in the next section 'Courses'. To view course abstracts please visit https://www.esda.org/training-and-education/esda-tutorials/

Pass An In-Depth Examination

The examination is online, consisting of multiple choice questions, following each course. You are required to pass each knowledge assessment with a grade of 80% or higher.

Cost

To enroll in this program, there is an official registration filing fee and exam fee of $125. Bundle price of $2,750 for all courses.

Enterprise License Options:

Certification Program

This Certification Perpetual License grants enterprise access to all courses in the ESD Design Engineer Certification 2 (EDEC2) certification program.

Click here for more information.

Specific Course

This Certification Perpetual License grants enterprise access to a specific course from the ESD Design Engineer Certification 2.

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How do I pay?

Purchase options for your organization:

Issue a Corporate PO, receive Invoice from EOS/ESD Association, Inc., execute payment

Individual Pay-complete personal purchase, receive receipt, request invoice from EOS/ESD Association, Inc., submit to company for reimbursement

Bundle PO or Invoice - Bundle multiple items for a corporate PO or purchase. Ask EOS/ESD Association, Inc. for an invoice form multiple attendees, memberships, standards, any of our products or service to process one time inside your company

DD117: TCAD: Fundamentals and First Applications to ESD

Technology computer-aided design (TCAD) tools have become an indispensable utensil for the semiconductor industry. The possibilities to analyze, predict and optimize a certain semiconductor device behavior through modeling semiconductor fabrication (process TCAD) and semiconductor device operation (device TCAD) are countless. This includes the area for ESD and latch-up development. Early access to fundamental device parameters under very high current density and high temperature transients is the key to overcoming the conceptual problem of concurrent engineering for ESD engineers.

This tutorial serves as a basic introduction to the TCAD toolchain, including process and device simulation and the creation and integration of compact models for mixed more simulation. Focus points are the capabilities and limitations of these tools, like the requirements for a 2D/3D simulation approach and the validity of the models describing the fundamental physics, especially in the high-temperature regime.

DD231: Physics, Testing, Debugging of Soft and Hard Failures

The tutorial is an expanded version of the previous DD231
tutorial on system level ESD. The main difference is the addition
of many experimental demonstrations, update of information,
and in-depth discussion on problems of the IEC 61000-4-2
testing, with examples on how to perform this testing and obtain
the best possible results and documentation. About half of the
time will be spent on experimental demonstrations.
Topics will include:
• ESD physics: charging and discharging.
• System level ESD testing
• System level soft failure mechanisms and debugging
• Design for avoiding ESD problems

DD381/382: Electronic Design Automation (EDA) Solutions for ESD and Latch-up

DD311: Impact of Technology Scaling on ESD Devices P1

This advanced tutorial will focus on high-current behavior
of stand-alone components, with the aim of optimizing
effectiveness of ESD clamp devices (irrespectively of their
schematic implementation) and maximizing the ESD SOA
(Safe Operating Area). Components in both Analog and Digital
technologies will be discussed, with emphasis on technology
trends. This class is intended for individuals who have taken
the basic on-chip protection class and are familiar with the
basic device physics for both ESD and latch-up.

DD317: Impact of Technology Scaling on ESD Devices P2

DD204: ESD Design in High Voltage Technologies

EDEC2-1: Integrated Circuits Reliability for ESD Engineers

DD300: Circuit-level Modeling and Simulation of On-Chip ESD Protection

This tutorial addresses modeling of on-chip ESD protection  devices and simulation of ESD protection networks. The  primary focus is SPICE-type simulation with compact (physics-based) models but a brief survey of other modeling approaches and simulation techniques will be provided. The physical operating principles of commonly-used ESD protection devices will be examined. The high-current characteristics and transient responses of those devices will be explored to ascertain what behaviors should be captured by
a model intended for circuit-level simulation of ESD. Specific examples of model implementations will be provided. Techniques for circuit-level modeling of self-heating will be presented. Parameter extraction and model scalability will be addressed. This tutorial assumes some familiarity with device physics. It is directed toward persons with interests in semiconductor device physics, electronic design automation, and on-chip ESD protection circuit design.

DD201: ESD Protection and I/O Design

This tutorial is intended to provide the attendees with the tools to take a device and circuit level understanding of ESD protection methods and implement them effectively in I/O designs for CMOS bulk technologies. Beginning with a review of common ESD protection strategies, this course will focus more directly on how to build ESD-robust I/O cells and how to integrate them on a full chip. The tutorial will cover various types of I/O pads including analog, RF and digital pads. Different types of ESD protection strategies and their usage in I/O pad cells will be described, for example rail clamp, self-contained, and SCR based protection schemes. This course will also discuss the decisions and challenges which ESD and I/O designers typically face when designing I/O pads. More complex ESD solutions will also be described such as stacked rail clamps, ghost rails, and protecting signals that can swing below ground or above the supply. Finally, this tutorial will touch on various supply schemes including multiple power domains and isolated grounding schemes. It will end with discussing pad ring construction aspects for both wire-bond and flip-chip packages.

DD150: Introduction to RF ESD Design

DD340: ESD System Level Simulation

Abstract
The tutorial is a hands-on training course for performing a simulation based optimization of PCB ESD protection design and provides deep understanding of the relevant performance criteria both of TVS diodes and IO circuits. The presented method follows the system efficient ESD design (SEED) approach as recommended by the Industry Council on Target Levels and JEDEC. The method allows the achievement of correct first time PCB builds and reduces the respin effort for boards and ICs. Based on a TLP characterization of SoC interface circuits and TVS diodes, simulation models for impedance and clamping behavior, as well as failure threshold, are extracted. These are used to assess design solutions by transient simulations. This is showcased by real world examples.

Learning outcomes
The attendee will understand the concept of SEED simulation and will be able to apply it to an own PCB /IC codesign simulation. This will allow the system design attendee to run a pre-hardware optimization of the board protection and it will enable the IC protection engineer to evaluate his protection concept regarding the available design window for system ESD

DD200: Charged Device Model Phenomena, Design, and Modeling

This course teaches basic ESD circuit design concepts and ideas required to design ESD protection for Charge Device Model ESD tests. The course covers a brief history of CDM ESD development, charge and discharge physics, characterization methods, CDM failures mechanisms, and CDM design-in strategies.

CDM ESD circuit design approaches and simulation setups for CDM failure debugging are presented in this tutorial on the basis of case studies. Insight into CDM circuit simulation requirements and physical aspects of the CDM ESD phenomenon that are important for reproducing the event with circuit simulation will be taught and modeling approaches for CDM specific device physical effects necessary for accurate circuit simulation will be introduced. This curse also teaches methods for simplified CDM circuit simulations where detailed information is either not available or too complex to simulate.

The course focuses on what type of circuits fail during a CDM discharge event and teaches the different types of ESD design circuit strategies that can be applied to protect those circuits. This class covers basic to advanced topics for CDM ESD design, but the student is assumed to already have a basic understanding of the CDM test method.

DD214: Latchup Physics and Prevention

Latchup has occurred in CMOS technologies since their
inception and continues as a threat in modern finFET
technologies. This course will begin with a basic overview of
the latchup phenomenon and then dig deeper into the theory
and physics associated with it. Latchup mitigation techniques
will be reviewed along with the physics behind them. These
will include both design and process techniques. The basics
and pitfalls of latchup testing will be taught, along with an
introduction into transient latchup. Proper wafer-level test
structure design and characterization will be taught.
The primary audience for this course is design and reliability
engineers tasked with designing for latchup success.
Latchup test engineers will also benefit from a deeper
understanding of latchup physics and design practices. The
course assumes some familiarity with basic circuit design
practices and semiconductor physics. Participants will leave
with a deeper understanding of the physics behind latchup,
its mitigation, and the impact of future technology trends on
latchup susceptibility.

DD302: Trouble-shooting on-chip ESD failures

Continuing Education & Renewal

To maintain certification, an annual renewal fee of $150 is required, along with the completion of 3 credits of ESDA Online Academy Design-Related Course. Alternatively, provide evidence of completing 3 hours of ESD Design-related instruction from another provider within the past 12 months.

How To Register

There is an official registration filing fee of $125.00 that must be completed and submitted to EOS/ESDA Association, Inc.