ESD TR22.0-02-18
ESD Association Technical Report for Relevant ESD Foundry Parameters for Seamless ESD Design and Verification Flow – Part 2 – ESD Parameters from Intellectual Property (IP) Providers
This document is intended to highlight the ESD-related issues relevant to intellectual property (IP) selection, IP on-chip usage, and IP integration verification. It addresses best practices which are consolidated between IP providers and IP users. Latch-up rules are only addressed as far as they are related to integration of ESD protection elements.
Table of ContentsAll electronic documents must be delivered directly to the intended person for use on only one computer. The document may not be forwarded to any additional users or accessed on multiple computers. Electronic documents will be emailed within 48 business hours.